Sezi
Junior Member level 2
Hello, I have some practical questions on the layout of mixed-signal circuits. I'll appreciate even if you only answer one of the following questions.. :idea:
1..:arrow: When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the drain/source area of the transistor, just beside the gate? Or is it better to extend the M1 outside of the MOS and put all the contacts on the extension?
2..:arrow: What's the most effective and best way to connect the fingered transistors' gates and other terminals to each other? I have read somewhere that connecting the gate fingers directly with poly is not a good idea?
3..:arrow: Is it better to start connecting the terminals other than vdd and gnd first with lower layer metals, and then in the end merging the vdd and gnd nets of all blocks with higher level metals? Is it better to use higher level metal for vdd/gnd?
4..:arrow: When making large layouts consisting of sub-blocks, how to achieve compact layouts with these sub-blocks with different sizes and shapes? Do we fill the spaces with bulk contacts? or how do we avoid these spaces?
5..:arrow: When making the layout of a PLL, is it better to group the digital components(PFD, divider..) and surround them with guard rings and place them apart from the analog blocks (VCO, charge pump, bias generator etc..)? What is the usual strategy?
Thanks in advance!
Sezi
1..:arrow: When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the drain/source area of the transistor, just beside the gate? Or is it better to extend the M1 outside of the MOS and put all the contacts on the extension?
2..:arrow: What's the most effective and best way to connect the fingered transistors' gates and other terminals to each other? I have read somewhere that connecting the gate fingers directly with poly is not a good idea?
3..:arrow: Is it better to start connecting the terminals other than vdd and gnd first with lower layer metals, and then in the end merging the vdd and gnd nets of all blocks with higher level metals? Is it better to use higher level metal for vdd/gnd?
4..:arrow: When making large layouts consisting of sub-blocks, how to achieve compact layouts with these sub-blocks with different sizes and shapes? Do we fill the spaces with bulk contacts? or how do we avoid these spaces?
5..:arrow: When making the layout of a PLL, is it better to group the digital components(PFD, divider..) and surround them with guard rings and place them apart from the analog blocks (VCO, charge pump, bias generator etc..)? What is the usual strategy?
Thanks in advance!
Sezi