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Please Have a Look.. Layout Questions..

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Sezi

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Hello, I have some practical questions on the layout of mixed-signal circuits. I'll appreciate even if you only answer one of the following questions.. :idea:

1..:arrow: When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the drain/source area of the transistor, just beside the gate? Or is it better to extend the M1 outside of the MOS and put all the contacts on the extension?

2..:arrow: What's the most effective and best way to connect the fingered transistors' gates and other terminals to each other? I have read somewhere that connecting the gate fingers directly with poly is not a good idea?

3..:arrow: Is it better to start connecting the terminals other than vdd and gnd first with lower layer metals, and then in the end merging the vdd and gnd nets of all blocks with higher level metals? Is it better to use higher level metal for vdd/gnd?

4..:arrow: When making large layouts consisting of sub-blocks, how to achieve compact layouts with these sub-blocks with different sizes and shapes? Do we fill the spaces with bulk contacts? or how do we avoid these spaces?

5..:arrow: When making the layout of a PLL, is it better to group the digital components(PFD, divider..) and surround them with guard rings and place them apart from the analog blocks (VCO, charge pump, bias generator etc..)? What is the usual strategy?

Thanks in advance!
Sezi
 

nightcat38

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1. okay to have contacts directly on drain/source
2. poly is not a good conductor
3. yes it is better
4. bulk contacts
5. you are right. other technique including metal shielding applied to the signal paths between digital and analog blocks
 

vlsi_whiz

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2. :arrow: Its best to connect fingered transistors using metal1 . Use more than one contact on the poly and then connect the gates together using metal.

3. :arrow: Generally, Metal 5 and 6 in a 6 metal process have larger thickness and should be used for VDD and VSS since these metal lines can handle more current than the rest. Its a good layout practice to have the even numbered metal layers go horizontal/vertical and the odd numbered metal layers go vertical/horizontal.

5. :arrow: When laying out PLL or other mixed signal blocks, always separate the analog and digital blocks and insulate the analog parts with guard rings as they are more sensitive to signal fluctuations. You should place the most sensitive analog part as far away as possible from the clock signals and digital parts. The rest of the analog parts can then be placed based on their sensitivity. Never run a clock signal or digital signal next to an analog one. If this cannot be avoided, insert a ground line in between the analog and digital signals.
 

vijay.kumarreddy

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1) U can place the contacts directly on the drain/source area.

2) Better connect with metal. If u connect with poly resistance will increase.

3)Of course, its correct,generally The VDD and GRD currents will be higher when compared to the circuit currents.Since higher level metals can handle high currents its recommended to use higher level metals for the VDD/GND connections.

4)The ompact layout can be achieved ewith the proper layout floor planning. Try to have ur inputs at the left side ,outputs at the right side And VDD/GND lines on the top and bottom of the blocks. sothat u can merge the VDD/GND s for different blocks.

5)Usually u need to place all the digital blocks together and analog and sensitive blocks together.Also u need to seperate the analog and digital grounds which is a must atherwise u will get the ground bounce problem..

Regards

vijay
 

leeenghan

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Hi,

Let me attemp on this not-so-easy question...

1. Switching metal layer on drain/source will allow more via without consume more area. I am not aware of any issue with this, except that if matching is important than it is good to do the same on the matching transistor

2. If you are using 1 or 2 metal layer than this is inevitable. Connecting with poly will also mean larger poly extension (on the connection side) to avoid flaring (refer to my book in www.eda-utiliteis.com). In general, the resistance of poly i s50-100 times more than metal, or 1um of poly inter-connect is equivalent to 50-100um of metal interconnect! If the poly-interconnect is long, than it might pick up too much parasitics capacitance, and also result in process antenna violation

3. Depend on you floorplan. Beware that metal1 can be much thinner than metal2.

4. Prepare to "re-shape" block-level layout to compact the top level. This is hard, but not-as-hard if you plan the top-level along the project, and the layout engineers are experienced. Typically, the reshape of the sub-block will take less-than-a-day to at most less than a few day. This i s a small investment compare to several week to draw the sub-block, and a end result that is beautiful. I suggest always put in the schedule a few days for reshape the sub-block when doing the top level (if you have several layout engineers working together, the reshape and top-level can happen together, and impact on schedule become small).

5. This is too diffcuilt to generalise. Do the best to isolate, not only between digital and anlaog, but also within the analog.

Regards,
Eng Han
www.eda-utilities.com
 

mahendra

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1.. When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the drain/source area of the transistor, just beside the gate? Or is it better to extend the M1 outside of the MOS and put all the contacts on the extension?

Depends on the application.If ur design demands the low resistance then later statement would work.Normaly we go with first line.

2.. What's the most effective and best way to connect the fingered transistors' gates and other terminals to each other? I have read somewhere that connecting the gate fingers directly with poly is not a good idea?

Metal connections on both the ends.

3.. Is it better to start connecting the terminals other than vdd and gnd first with lower layer metals, and then in the end merging the vdd and gnd nets of all blocks with higher level metals? Is it better to use higher level metal for vdd/gnd?

Ya u r right

4.. When making large layouts consisting of sub-blocks, how to achieve compact layouts with these sub-blocks with different sizes and shapes? Do we fill the spaces with bulk contacts? or how do we avoid these spaces?

If u r floorplan shows the un avoidable space in the design then u may fill with bulk contacts or u may use it for DUMMY METAL FILL.

5.. When making the layout of a PLL, is it better to group the digital components(PFD, divider..) and surround them with guard rings and place them apart from the analog blocks (VCO, charge pump, bias generator etc..)? What is the usual strategy?

Tht's good idea to keep distance&Guard rings.

Regards
Mahendra
 

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