Alauddin123
Newbie level 5
Hello All,
I came across the option of adding register pipeline stages(1,2,3) while generating the BRAM IP via coregen. can any one explain me in detail how this additional regs improve the performance of the core ?
I came across the option of adding register pipeline stages(1,2,3) while generating the BRAM IP via coregen. can any one explain me in detail how this additional regs improve the performance of the core ?