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High speed ADC with FPGA and base band processing

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Full Member level 3
Mar 13, 2015
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Hello all,

I've got a sort of spectrum analyzer circuit I've been working with that operates at an IF of ~27 MHz and currently it's almost entirely analog. However, I was looking to convert the IF's output to a digital signal path. My aim was to use a high speed (I realize high speed is quite the relative term) ADC to digitize the 27 MHz IF and implement many of the base band functions: bandwidth resolution filter, logarithmic amp, power detection method, LPF Video filter, and final output, to a digital signal path. This would give me much more functionality than I currently have given the analog circuits are quite static. I currently use a cheap microprocessor to control all the analog switches and read the final power out from a very low speed ADC, however, I can't use that same processor to interface with an ADC running at a sample rate greater than 54 MHz.
I have never used an FPGA (now is as good a time as any to learn) before but I've been doing some reading into possibly using one to help read in the output of an ADC and perform all the different processing steps listed above. I had a few questions I wanted to run by some more experienced folks before investing too much time and effort into this endeavor.
My first question is more general: Is something like this possible to do in real time? I've been looking to using FPGA development kits to start, ones with on board RAM, crystal oscillators, many GPIO ports. Given the available different free softwares out there (ie: Vivado), are there blocks that implement functions such has filters, amplifiers, and functions to compute RMS or average values?
More specifically: I've been looking at the Arty A7: Artix-7 FPGA Development Board (I am happy to hear of better alternatives). Mostly because there is a lot of documentation, online help available, and the board is actually available to buy. Looking through the reference manual, Xilinx has a clock wizard IP block that can create a reference clock which I would need for an ADC. Is that generated reference clock something I could program to be routed to a GPIO port while also programming the adjacent GPIO ports to be GND? Or would that reference clock be limited to use within the FGPA itself?
Less specificity to FPGAs: are there limitations to implementing digital filters? Would I be able to have digital bandwidth resolutions filters with pass bands on the order of 30 KHz at a center frequency of 27 MHz?
Lastly, any general tips, advice, pitfalls, or criticisms of my plan would be much appreciated.

I realize that is a lot to ask in 1 go, so thanks in advance for any help,

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