FlyingDutch
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Hello Guys,
i have one issue with VHDL code. The prooblem is related to multiple drivers. I have in some place of my code such fragment (VHDL):
In this process i am setting saveCycle <= '1'; - which means that there is need to write last data chunk to BRAM memory. And in next process I am checking this signal saveCycle and if it is equal '1' I am writing data chunk to BRAM - see code:
After saving data to BRAM I set saveCycle <= '0'; in order to not save data to BRAM next time. But this cause error:
Could I ask more experienced colleagues to advice me how to properly organize such data processing?
Thanks in advanvce and regards
i have one issue with VHDL code. The prooblem is related to multiple drivers. I have in some place of my code such fragment (VHDL):
Code:
PROCESS (lpc_en, lclk)
BEGIN
IF (lpc_en'EVENT AND lpc_en = '1') THEN
cycle_cnt <= cycle_cnt+1;
IF (cycle_cnt >= 8) THEN
cycle_cnt <= 1;
sendPackage <= '1';
IF (packageNumber = 1) THEN
packageNumber <= 2;
package2Send <= 1;
ELSIF (packageNumber = 2) THEN
packageNumber <= 1;
package2Send <= 2;
END IF;
-- zapisz do BRAM ostatni cykl + wyślij 8 poprzednio zapisanych
ELSE
-- tylko zapisz do BRAM ostatni cykl
sendPackage <= '0';
END IF;
addrAbufU <= to_unsigned(((packageNumber-1)*8+cycle_cnt-1),addrAbufU'length);
addrAbuf <= std_logic_vector(addrAbufU); --adres zapisu w BRAM
---------------
lpc_addrBuf <= lpc_addr;
lpc_data_inBuf <= lpc_data_in;
--wykonaj zapis do BRAM pod wskazany adres
saveCycle <= '1';
END IF;
END PROCESS;
In this process i am setting saveCycle <= '1'; - which means that there is need to write last data chunk to BRAM memory. And in next process I am checking this signal saveCycle and if it is equal '1' I am writing data chunk to BRAM - see code:
Code:
PROCESS (lclk, lreset_n) --save current cycle in BRAM
BEGIN
IF (NOT lreset_n = '1') THEN
cnt2 <= b"0000000000000";
ELSIF (lclk'EVENT AND lclk = '1') THEN
IF (saveCycle = '1') THEN --trzeba zapisac aktualny cykl do BRAM
if (cnt2 = 0) then
cnt2 <= cnt2 + 1;
elsif ((cnt2 > 0) and (cnt2 < 10)) then
cnt2 <= cnt2 + 1;
enaB <= '1';
weaB <= "1";
dinAbuf(31 downto 28) <= "0000";
dinAbuf(27 downto 12) <= lpc_addrBuf;
dinAbuf(11 downto 4) <= lpc_data_inBuf;
dinAbuf(3 downto 2) <= "00";
dinAbuf(1 downto 0) <= std_logic_vector(cycle_type);
elsif ((cnt2 >= 10) and (cnt2 < 14)) then
cnt2 <= cnt2 + 1;
weaB <= "0";
saveCycle <= '0';
end if;
END IF;
END IF;
END PROCESS;
After saving data to BRAM I set saveCycle <= '0'; in order to not save data to BRAM next time. But this cause error:
Code:
[DRC MDRV-1] Multiple Driver Nets: Net saveCycle has multiple drivers: saveCycle_reg__0/Q, and saveCycle_reg/Q.
Could I ask more experienced colleagues to advice me how to properly organize such data processing?
Thanks in advanvce and regards