manissri said:hi neoflash,
actually if the input full range is suppose -verf to +verf ,
then ur residue will lie between -1/2verf to +1/2verf
and there is a region of -1/2 vref and +1/2vef for residue moment.
means if there is an subadc offset upto +1/2lsb r -1/2lsb( -1/4vref r +1/4vref)
then ur residue will shift and the residue will remain in -verf and +vref for the next stage.
so the sub adc error upto 1/2lsb(+ and - both) can be tolerated by 1.5 bit adc.
and if this error occours in subadc then this will be taken care in digital error correction ckt used in adc.
so this is the beauty of 1.5 bit pipelined adc.
hope this help.
regrds
manish
The resulting difference is greater than vref*1/2 adn get outside of the processing range of the subsequent stages. So the size of the error define the amount of missing code or overlap.
manissri said:Hi neoflash ,Rfsystem
some basics i need to clear too regarding pipelined adc.
hope u all will dont mind.
actually in 1.5 bit pipelind adc , the residue passes from one stage to next stage.
then our residue is getting smaller and smaller and in last stage it is very small.
but in stage we give the gain of two so that residue will be in the full range of input.
but my question is when we give every stage gain of two then our residue will multiply by 2 then where it is gettin smaller and smalller when it passes stage to stage.
plz give ur comment.
regrds
manish
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