Pipe-line ADC redundant bits

[neoflash]

Can anyone help explain all the benefits of redundant bits in pipeline ADC?

Added after 14 minutes:

While reading a lecture on Pipe-Line ADC design, it asserted that redundancy in pile-line ADC converter will help reduce the chance of having missing code issue.

It asserted that we can tolerate sub-adc error if previous stage's residue is kept below the "BOX" of next stage's input. The box refered to as full-scale voltage of ADC.

Do you agree on that?

 

[sankudey]

The redundant bits in pipeline stages are used for error correction, which is a post process after the digital bits of the ADC are available.....the error correction in digital domain helps to correct the error (hence increase accuracy) coming from the analog parts.....this directly helps in relaxing the comparator offset.....

for details u can go thru the following reference....

1. Digital techniques for improving the accuracy of data converters
Un-Ku Moon; Temes, G.C.; Steensgaard, J.;
Communications Magazine, IEEE
Volume 37, Issue 10, Oct. 1999 Page(s):136 - 143
Digital Object Identifier 10.1109/35.795604

Summary: This article provides a tutorial overview of some previously developed methods for enhancing the accuracy and linearity of data converters (analog-to-digital as well as digital-to-analog) by introducing auxiliary digital circuitry which calibrates, c.....

AbstractPlus | Full Text: PDF(692 KB) IEEE JNL


---------------------------------------------------
If u need the paper...can write to me....

sankudey

 

[neoflash]

thanks.

could you please put the paper here?

Also, author put her comments here below:

 

[manissri]

hi sankuday.
plz uplaod that paper ..
it will be help ful to me if u could plz send it
regrds
manish

Added after 14 minutes:

hi neoflash,
actually if the input full range is suppose -verf to +verf ,
then ur residue will lie between -1/2verf to +1/2verf
and there is a region of -1/2 vref and +1/2vef for residue moment.
means if there is an subadc offset upto +1/2lsb r -1/2lsb( -1/4vref r +1/4vref)
then ur residue will shift and the residue will remain in -verf and +vref for the next stage.
so the sub adc error upto 1/2lsb(+ and - both) can be tolerated by 1.5 bit adc.
and if this error occours in subadc then this will be taken care in digital error correction ckt used in adc.
so this is the beauty of 1.5 bit pipelined adc.
hope this help.
regrds
manish

 

[rfsystem]

The magic 1.5bit per stage seems to facinate many people.

It is of historic importance!

Today radix or pipeline designs are focused on true engineering, not on research. The implementation try to minimize area and current by providing reasonable production yield. The key is to decide about no error correction, wafer test correction, powerup time correction or background correction. And to choose the right number of bits for each stage. There is a trade of the size/current of each stage versus bits and the total.

1.5bit is not used in production in current techs up to my knowledge.

 

[neoflash]

hi neoflash,
actually if the input full range is suppose -verf to +verf ,
then ur residue will lie between -1/2verf to +1/2verf
and there is a region of -1/2 vref and +1/2vef for residue moment.
means if there is an subadc offset upto +1/2lsb r -1/2lsb( -1/4vref r +1/4vref)
then ur residue will shift and the residue will remain in -verf and +vref for the next stage.
so the sub adc error upto 1/2lsb(+ and - both) can be tolerated by 1.5 bit adc.
and if this error occours in subadc then this will be taken care in digital error correction ckt used in adc.
so this is the beauty of 1.5 bit pipelined adc.
hope this help.
regrds
manish

thanks for the inputs. I understand that 1.5Bit could reduce residue amplitude inside next stage's input range. However, still thank you that make it that clear.

My two remain questions are:
1. From 1.5Bit stage, we got two bits. I think they are all useful. We should use digital logic to compute final results from both of them. So, it is not really redundant, right?

2. What's 1.5Bit's advangate on missing code? How it attacks missing code issue?

thanks,
Neoflash

 

[rfsystem]

Hi neoflash,

let me explain in more detail the "beauty" of the 1.5bit pipeline.

The 1.5bit is coming from the radix description. In nonerror correcting pipeline ADC each stage substract/add a value which 2^(-1) times the single side input scale or 2^(-2) the double side input scale. For instance if the input is -vref...vref, the radix value of the first stage is -vref*2^(-1) or vref*2^(-1). If in the second processing cycle the gain is 2 then the input scale is equal in all stages. This construction is using the radix factor 2. If you use radix factor 1.5, which does not mean you 1.5bit, the radix value is -vref*1.5^(-1)=-vref*2/3 or vref*2/3.

If the radix value of the first stage has an error. For instance +1e-3. So that the real positive radix is vref*(1/2+1e-3). If the input to the ADC is between 0 and vref*1e-3 then the comparator of the first stage decide to substract the positive radix value. The resulting difference is greater than vref*1/2 adn get outside of the processing range of the subsequent stages. So the size of the error define the amount of missing code or overlap.

If the radix ifactor is smaller than 2 a mismatch does not result in exceeding the signal ranges. Anaway a exact digital representation of the radix value should be used because the digital output of the pipeline ADC is the sum of all digital radix values. In the trivial case these are only powers of 2. So each stage of the comparator set one bit. For non radix factor 2 you use for instance either

-vref*(2^(-1)+2^(-k)) or -vref*(2^(-1)+2^(-k))

with k low enough to cover tolerancies.

For multibit pipeline you have more than 2 radix values. With digital calibration you could have also nonequal spacing between the different radix values for each stage.

If for instance the radix value could have 5 different values how many bits per stage is this?

You see that the magic beauty of 1.5 is not 1.5bit but the radix base number is 1.5!

SILICON is where MATH meet PHYSICS

 

[neoflash]

I am getting a little bit lost.

I still want to focus my two questions.

1st question can be expressed in another form:
1bit overlap pipelined ADC will used attched graph way to combine redundant bits, how 1.5bit combine that half bit?


By the way, you said:

The resulting difference is greater than vref*1/2 adn get outside of the processing range of the subsequent stages. So the size of the error define the amount of missing code or overlap.

Can you prove that there is a relationship between missing-code and "extre residue"?

 

[manissri]

Hi neoflash ,Rfsystem
some basics i need to clear too regarding pipelined adc.
hope u all will dont mind.
actually in 1.5 bit pipelind adc , the residue passes from one stage to next stage.
then our residue is getting smaller and smaller and in last stage it is very small.
but in stage we give the gain of two so that residue will be in the full range of input.
but my question is when we give every stage gain of two then our residue will multiply by 2 then where it is gettin smaller and smalller when it passes stage to stage.
plz give ur comment.
regrds
manish

 

[neoflash]

Hi neoflash ,Rfsystem
some basics i need to clear too regarding pipelined adc.
hope u all will dont mind.
actually in 1.5 bit pipelind adc , the residue passes from one stage to next stage.
then our residue is getting smaller and smaller and in last stage it is very small.
but in stage we give the gain of two so that residue will be in the full range of input.
but my question is when we give every stage gain of two then our residue will multiply by 2 then where it is gettin smaller and smalller when it passes stage to stage.
plz give ur comment.
regrds
manish

Yes. I also have this question.

I've ever seen several papers only use 1.5Bit stage in most critical stages, instead of using them all. However, it seems in 2005 ISSCC, some Janapese presented 10 stage adc all using 1.5Bit. I've not read the paper yet.

Hope someone else could elaborate it.

 

[rfsystem]

I check some papers and found some doubleuse of the 1.5bit term. It is used to first describe a 2-level radix with 3 decision codes, second to describe a 2-level radix with only 2 decision codes. The first reference interprete the 3 codes as 1.5bit, the second interpretation is the radix base.

1. 1.5bit code version
input range -1...+1, codes:

if input < -r
code=a
ifelse input > -r & input < r
code=b
else
code=c
end

if code=a
y=2*(x+r)
elseif code=b
y=2*x
else
y=2*(x-r)
end

r=1/3, so spacing between radix levels and range borders is 2/3

2. 1.5 radix base version
input range -1...+1, codes:

if input < 0
code=a
else
code=b
end

if code=a
y=2*(x+r)
else
y=2*(x-r)
end

The version1 use 2 comparators. The version2 only 1 comparator.

If there is a missing code it would impact the input range around -1/3 or 1/3 for the version1. The version2 will be impacted around zero. If no correction is done the version1 have SNDR advantages at low input levels. That is because the most critical gain or level mismatch is outside the critical input range for low level signals.

Independend from both versions the digital code have to composed by sequential addition of the numeric representation of the radix values.

 

[thomasross20]

Hi, I'm new here..

I'm doing some work on pipelined ADCs and have just come across the whole 1.5bit stage/ digital error correction arena.. To be honest, I'm very confused!! Reading the above didn't really help, sorry!

So there are 3 ranges.. -Vr to -Vr/4, -Vr/4 to Vr/4, and Vr/4 to Vr. This corresponds to the input signal, or residue from previous stage. The codes which can be assigned to these are 00, 01, 10 (or should 10 be 11? The output from the flash WILL be a thermometer code, so maybe 11 makes more sense).

Now.. Take the first section (-Vr to -Vr/4).. the operation yuo perform on the input is 2Vin + Vr. Middle section: 2Vin. Top section: 2Vin - Vr/4.

Things I'm confused abuot:

If Vr = +/- 0.5V (so full-scale = 1V), then for Vin = -0.5V, the residue is [2*(-0.5)] + 0.5 = -0.5 (Or -Vr = 2LSB, I believe)!! However, in most papers I've seen, the residue only goes from -Vr/2 to +Vr/2! Help??

Why are the levels set at Vr/4? Do they have to be?

The correction circuitry is used to keep the residue within the conversion range of the next stage, rather than being able to detect an incorrect output based on a comparator offset?

If there is a comparator offset and the residue increases, the input of the next stage will still be within +/-Vr, so all will be OK? But wont this residue continue to escalate until it goes out of range of all future stages?

I don't really understand how the 1.5bit/3-level, with 0.5bit redundant data actually helps us..??

How on earth is the correction circuitry actually constructed? I read that some people use some adders and bit-overlap, and some use other techniques.. will it be more difficult for higher res stages? I need some circuits to look at

There seems to be very little actual circuitry and explanation on this; I've read a LOT of papers on it, but there is nothing substantial out there; even the papers by S.H.Lewis proved to be of limited help.

Thanks VERY much for any help on this... I would REALLY appreciate it!!!

 

[jerryzhao]

I try my best to explain this question.
I give you a example.
If a 10 bit pipeline ADC, no digital error correction, 1bit/stage
The stage1 is responsible the 10-th bit
The stage2 is responsible the 9-th bit
... it is easy to understand.
If 2bit/stage and no digital output overlap.
The stage1 is responsible the 10-th and 9-th bit
The stage2 is responsible the 8-th and 7-th bit
... it is easy to understand too.
But that need the comparator have good accuracy.

If ther are overlap every stage. it can tolerance the comparator's offset, as the overlap each stage. example: 2b/stage but overlap
The stage1 is responsible the 10-th and 9-th bit
The stage2 is responsible the 9-th and 8-th bit
...... It must be overlap added then get right number of output code.
The overlap added can tolerance the comparator's offset, but it contribute a offset too when you use (-1/2 1/2) decision line. In order to remove the overlap added's offset we can change to decision line to (-1/4 1/4).

It is not easy to explain those questions.
I hope you can reference CMOS data converters for communication p235-239 .

 

[Mazz]

Very interesting discussion, thanks to RFsystem.

Any comment on 2.5 bit Pipeline ADC?

Mazz

 

[thomasross20]

Does a pipeline ADC using SC MDAC and ADSC even need a sample and hold at the input?

 

[rfsystem]

No,

most implementation use sample/hold and radix within a first single stage. There is no specific advantage of use tow separate stages for this operation. That is because the power consumption because of noise is the highest in the first stage.