phase margin issue with a positive feedback in current mirror OTA

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I think my comments are invisible, the output impedance doesnt change, because hes adding a parallel rds to a 1/gm, 1/gm will win without much budge.
the gain is as the book says a ratio of the pos fb and the neg fb(bad things can happen when the ratio =1). the reduced pm is due to the added cgs and cds on the drain of the input pairs, which impacts both pole1 and pole2.
to calculate the actual pole change you need to do the math,
1)create the small sig equation for vout over vin while keeping all the caps (including the miller Cgd cap)
this will give you a numerator and denominator with s terms on bottom and possibly top. rearranging these terms should give you an s term polynomial
1b) the denominator form should be s^2A + sB + 1, i would ignore any s^3 terms if you have any.
2) pole form = s^2/(p1 * p2) + s/(p1) +1
pole 1= 1/B
pole 2 = 1/(A*pole1)
 

Thank you LvW very much

Actually I told you about the load capacitor from the previous post (Load is purce capacitive with CL=50 PF).

this paper is useful

this paper is useful I think



 

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