[SOLVED] phase detector not working

[mggayathrimg]

sir
We are using D flipflop logic for implementing phase detector in PLL.But even after reseting, the outputs(up & down signals) of the phase detector are oscillating.Can you please suggest some solutions to this.







<a title="pll.png" href="http://obrazki.elektroda.pl/2262646000_1349847714.png"><img src="http://obrazki.elektroda.pl/2262646000_1349847714_thumb.jpg" alt="pll.png" /></a>

 

[chuckey]

Without a circuit it is impossible, I would add is there enough decoupling on the Vcc line?
Frank

 

[mggayathrimg]

This is the circuit we used.

 

[mdeepak12]

The best way to debug is to use an ideal D flipflop (Verilog A model).

Some capacitance/frequency problem I guess!!!

 

[chuckey]

I think the problem is that the reset line is not edge triggered. When the Q output goes high the reset goes high , causing the Q to go low, which releases the reset so Q goes high again. . . .
Frank

 

[FvM]

Apart from the problem, that the asynchronous reset may cause a timing violation (e.g. being too short), some artefacts in the simulation waveforms suggests a serious hardware problem, e.g. the reset spike occuring on the first clock edge. In so far, post #2 seems to hit the point.

 

[AdvaRes]

Reset signal change when A change. The and gate is not well designed.