sir
We are using D flipflop logic for implementing phase detector in PLL.But even after reseting, the outputs(up & down signals) of the phase detector are oscillating.Can you please suggest some solutions to this.
I think the problem is that the reset line is not edge triggered. When the Q output goes high the reset goes high , causing the Q to go low, which releases the reset so Q goes high again. . . .
Frank
Apart from the problem, that the asynchronous reset may cause a timing violation (e.g. being too short), some artefacts in the simulation waveforms suggests a serious hardware problem, e.g. the reset spike occuring on the first clock edge. In so far, post #2 seems to hit the point.