PCB Trace Width Suggestion - 3A LiPo Charger

[sakibnaz]

Hi there.

I am designing a Single Cell Li-Po Charger supporting 3A Charge current. I choose MP2617BGL-Z Charge Controller IC.

MP2617B

3A Switching Charger with NVDC Power Path Management For 4.2V Single Cell Li+ Battery

www.monolithicpower.com

Now I have a ques about PCB Design mainly Tare Width. The PCB Pad size of the IC VBAT pin is around 55mil x 10mil. So my Trace min width will be less than 10mil. Then how can it carry 3A current?

According to https://www.4pcb.com/trace-width-calculator.html Width needs to be 140mil.

Also I checked the official Evaluation Kit design their min Trace will be less than 10mil as well close to the IC Pad.

Please advise how to do the design.


Thanks in advance.

Regards.

 

[FvM]

Why do you refer to inner layers calculation, a trace connecting a SMD pad is obviously on outer layer, unless you use VIPPO (via-in-pad plated over) technology. It's also quite normal to have short tapered trace segments to connect a pad. Design rule check won't count it as a trace width violation.

 

[Carry for cents bazar]

Put multiple tracks on different or the same layer. Put a wire.

 

[sakibnaz]

Hi @FvM ... sorry I mistakenly marked the inner layer. But still the outer Layer needs 53.8mil Trace width where as the Pad width is 10mil? How to achieve that?

@Carry for cents bazar, I did not understand what you mean by "Put multiple tracks on different or the same layer. Put a wire. ", can you please explain?

Thanks.

 

[FvM]

Trace width design rules are valid for traces of certain length, not for very short segments.

You can
1. Use the evaluation board layout and assume that it's designed correctly
2. Calculate resistance and power dissipation of the tapered trace structure to determine if it's feasible.