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Calculating PCB trace length for USB and UART

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engr_joni_ee

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Hi, in the document "UltraScale Architecture PCB Design UG583 (v1.25)", the requirements for PCB and package delays are described on page 180, see attachment.

I am calculating the PCB trace length with the given time in attachment and by considering the speed of signal in FR4 15 cm /ns.

UART
• Keep MIO trace delays below 1.30 ns: Does this means that the PCB trance length on Tx and Rx should be within length = speed x time = 15 cm / ns x 1.3 ns = 19.5 cm ?

USB 2.0
ULPI Interface (60 MHz)
• PCB and package delays should be kept to 1.30 ns or below: Does this means that the PCB trance length on USB signals should be within length = speed x time = 15 cm / ns x 1.3 ns = 19.5 cm ? • PCB and package delay skews for DATA[7:0]/DIR/NXT/STP and CLK should be within ±100 ps: Is that related to the length matching ? Meaning that the length mismatch between USB signals has to be within length = speed x time = 15 cm / ns x 0.1 ns = 1.5 cm ?
 

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Hi,

sadly you just give a screenshot, a tiny bit of a datasheet.

UART: My first question: what does MIO mean? It talks about MIO trace length.
Considered that UART cables can be several meters long ... I don´t see why the Rx and Tx trace length should be restricted.

Klaus
 

Hi, MIO is multiplexed I/O at the processor available on ZYNQ and I guess the are talking about the length of traces and delays on the PCB and not the external cables. The document "UltraScale Architecture PCB Design UG583 (v1.25)" is actually a PCB design guide for ZYNQ Ultrascale.
 

I’m with Klaus, I can’t see any reason for that 1.3nS delay limit. But, a PCB trace has a nominal delay of 85 pS/ inch, so you can have a pretty long trace and still meet this requirement.
 

Hi,

I guess the are talking about the length of traces and delays on the PCB and not the external cables.
What´s the idea behind it?
What´s the difference of trace length on a PCB and a wire length in a cable?
What´s the difference if the delay is generated on the PCB and in the cable?

Delay of a Tx or Rx signal does not matter at all in an asynchronous UART interface.

Without further information .. I call such restrictions as nonsense.

Klaus
 

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