Passing pPar() value from schematic to layout and Illegal weak-connect connection.

[melkord]

I have some questions about analog layout and the software.

1. I got incorrect MOSFET size if the schematic drawing uses pPar() to hold and pass some parameters. pPar() works nicely with ADEL. Am I missing something here?

2. My layout has blinking illegal weak-connect connection line even though it passes DRC. I have not done LVS, because it is not yet finish. I do not know what I should do to solve this.

3. When should I use guard ring? My LNA consists only 4-6 MOSFETs. Using guard ring increases area consumption by 10-30 % (rough estimates). Is it a good decision to use guard ring in this situation?

 

[dick_freebird]

You would need the params referenced by pPar()
to be set. This might bother any attempt to lay out
the "dependent" block, in isolation, from the same
level schematic. You might need to make a higher
level "wrapper" schematic that just has an instance
of the target block placed with properties filled. And
then a similar layout hierarchy, with the "real" layout
placed under the "wrapper" and edit-in-place.

Discard the wrapper when done.

Or, fix the schematic to make fixed params if
you know what they are supposed to be. Is the
layout to be parametric as well? Or are the
params just vestiges of the design phase, left
dangling?

I know we used to make parametric
symbol/schematic/layout cells for logic and
used this functionality. But it was long ago and
who's to say things have gotten better instead
of "worse enough that you'll pay more for the
next generation tool that does what the cheaper
one used to" (it's Cadence, after all, and their
motives and practices are well known).

Now I have a vague notion that layout views
may use a different form of argument passing
to PCells, than pPar() but can't recall specifically
or say whether I'm mis-imagining.

Guard rings are a good way to make the body
of the FETs resist the D-B capacitance and its
seldom-helpful effects on linearity. 10%-30%
of area seems high, I guess this circuit has no
pads.

 

[Dominik Przyborowski]

1. You have to create parameterized layout. Usually, it's much more work so people does not doing this. However, "Virtuoso Relative Object Design User Guide" is your friend here.

2. Weak connection exists when some terminals are connected by non conducting layer. Common case of lack of guard rings for body.

3. Always.

 

[melkord]

You would need the params referenced by pPar()
to be set. This might bother any attempt to lay out
the "dependent" block, in isolation, from the same
level schematic. You might need to make a higher
level "wrapper" schematic that just has an instance
of the target block placed with properties filled. And
then a similar layout hierarchy, with the "real" layout
placed under the "wrapper" and edit-in-place.

Discard the wrapper when done.

Or, fix the schematic to make fixed params if
you know what they are supposed to be. Is the
layout to be parametric as well? Or are the
params just vestiges of the design phase, left
dangling?

I know we used to make parametric
symbol/schematic/layout cells for logic and
used this functionality. But it was long ago and
who's to say things have gotten better instead
of "worse enough that you'll pay more for the
next generation tool that does what the cheaper
one used to" (it's Cadence, after all, and their
motives and practices are well known).

Now I have a vague notion that layout views
may use a different form of argument passing
to PCells, than pPar() but can't recall specifically
or say whether I'm mis-imagining.

Guard rings are a good way to make the body
of the FETs resist the D-B capacitance and its
seldom-helpful effects on linearity. 10%-30%
of area seems high, I guess this circuit has no
pads.

I have made an instance and filled the parameters of that instance with the expected values. Then, I tried to create the layout from this higher level schematic, still it does not work as I expected. It seems that there is no other way than pluging in the values directly to the MOSFETs' sumbols.

I am not sure whether making layout using "create from source" method is parametrized. But this is the method I am doing. I do not draw every single layer manually. I just click "create from source" icon and, if the parameter values are plugged in directly to the MOSFETs symbols instead of using pPar(), I got the layout for that MOSFET drawn automatically with correct size and #finger.

thanks for your suggestions.

1. You have to create parameterized layout. Usually, it's much more work so people does not doing this. However, "Virtuoso Relative Object Design User Guide" is your friend here.

2. Weak connection exists when some terminals are connected by non conducting layer. Common case of lack of guard rings for body.

3. Always.

1. Thanks, I will take a look of that doc.
2. I solved it. I forgot to connect one ground to the other grounded nodes.
3. thanks.