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illegal weak connection warning in layout

Junus2012

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Hello,
I am designing serial shift register, I have noticed after the 16 bit length the Cadence "Check against Source" in Layout GXL tool give me connectivity warning about illegal week connection.
However my design passed successfully the DRC and the LVS and the post layout simulation is running perfectly.

But I am not sure if this warning is harmful or I can live with it

Please see the attached image, I have traced one of the weak connection

Best Regards
2.png
 

dick_freebird

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Some kits flag connections made through poly or diffusions as "weak". Whether they add much "weakness" to a near minimum width transistor's drive, is a question that the flag is meant to focus you on.

Weak connection through psub or nwell for supplies would be bad. 10 ohms of silicided poly jumper might be a good layout trade if it removes a met2 routing blockage in a std cell. In that case representing the region as a PDK blessed resistor might be the path to clean reports.
 

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