Parasitic capacitors between clock wires? (analog layout)

[metuo_abeo]

Hi,

I want to make the layout for a sample&hold circuit that involves the autozero technique. My question is how to avoid possible dc coupling (and other effects like cross-talk) between these signals (non-overlapping signals). It's a good idea to add some parasitic capacitors in the schematic between the clock signals or between the input signal and clock signal?

PS: I use transmission gates as switching circuits.

Thanks!

 

[arthorios]

To avoid coupling from your clocks to any other signal, you can always shield them. A common way of doing this is by using on-chip "coaxial cables."
For example, if you run your clock signals in M2, shield them with M1 (below) and M3 (above) and add vias from M1-to-M3 around them. M1 and M3 are then connected to ground. You might need to have stronger buffers to drive the clock lines due to parasitic capacitances, though.

 

[metuo_abeo]

Thank you for your answer! So, my point (to add some parasitic capacitors in the schematic between the clock signals or between the input signal and clock signal) it's not a good idea.

 

[IQ_drift_3σ]

It's very depends on freq of your circuit, and waht's around. But the basic approach it's split them in different layout metals and move them away from these metals. BTW arthorios approach is great example, but might be overwhelming for this situation. Shielding is good for differentials signals, adding a constant cap of vdd/vss for net can make signal very resistive from other flickering-noisy signals. Also, remember, that cap depend's of bus width, and distance between bus of the same metals. Anyway the final tuning is after layout extraction and post-layout simulation. You can check this entry level book for more:"IC Mask Design - Essential Layout Techniques" - C. Saint, J. Sasint.