May 7, 2015 #1 S srikanth408 Newbie level 2 Joined Feb 3, 2015 Messages 2 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 13 According to JEDEC standard, in source synchronous systems like ddr2 there is no limit on filght time between two ICs and no limit on Clock skew. How is it possible in ddr2 and not possible in ddr
According to JEDEC standard, in source synchronous systems like ddr2 there is no limit on filght time between two ICs and no limit on Clock skew. How is it possible in ddr2 and not possible in ddr
May 7, 2015 #2 D.A.(Tony)Stewart Advanced Member level 7 Joined Sep 26, 2007 Messages 9,005 Helped 1,823 Reputation 3,645 Reaction score 2,197 Trophy points 1,413 Location Richmond Hill, ON, Canada Activity points 59,567 Where does it say this? https://www.jedec.org/sites/default/files/docs/JESD230B.pdf