overcome limit on flight time and clock skew in source synchronous systems

[srikanth408]

According to JEDEC standard, in source synchronous systems like ddr2 there is no limit on filght time between two ICs and no limit on Clock skew. How is it possible in ddr2 and not possible in ddr

 

[D.A.(Tony)Stewart]

Where does it say this? https://www.jedec.org/sites/default/files/docs/JESD230B.pdf