[SOLVED] i need help making a 24 h adjustable digital clock with 74192 and 7447 and 7 segment on Proteus

[shirotpoison]

so i have 2 counters for seconds an 2 counters for munits the problem is how to connect the second block with the munits block ,when i add a AND gate it glitched the munits counter hits 1 on 40 second , i add an RC circuit it make seconds reech 60 but the munits steel go 1 on 40 seconds , So any solution of how to connects the two blocks together correctly

 

[barry]

perhaps a schematic?

 

[shirotpoison]

perhaps a schematic?

so i have 2 counters for seconds an 2 counters for munits the problem is how to connect the second block with the munits block ,when i add a AND gate it glitched the munits counter hits 1 on 40 second , i add an RC circuit it make seconds reech 60 but the munits steel go 1 on 40 seconds , So any solution of how to connects the two blocks together correctly

 

[shirotpoison]

perhaps a schematic?

 

[BradtheRad]

From your schematic U10 (AND gate) goes high when the count reaches 6, resetting U3 (counter) to zero.

I believe that same signal is supposed to be connected to increment U5 (counter) by 1 minute. Even if you connected it...
The signal goes through 100 ohms to 100 uF to ground. Those values draw away current which may cause voltage to sag on the wire at the very instant it's supposed to increment U5. I think R15 resistance should be greater. And C1 should be lesser.

 

[barry]

As BtR points out, you're missing a clock connection to the minute counter. But I don't even see the point of that HUGE RC. You've turned a digital circuit into an analog circuit and you've added a glitch: the second counter counts to 6 and then resets itself, so your display will probably flicker.

 

[shirotpoison]

From your schematic U10 (AND gate) goes high when the count reaches 6, resetting U3 (counter) to zero.

I believe that same signal is supposed to be connected to increment U5 (counter) by 1 minute. Even if you connected it...
The signal goes through 100 ohms to 100 uF to ground. Those values draw away current which may cause voltage to sag on the wire at the very instant it's supposed to increment U5. I think R15 resistance should be greater. And C1 should be lesser.

i did counted the u5 with the and gate , it hits 1 when 40 seconds , so what the values of RC do you suggest

 

[KlausST]

Hi,

this sounds like a school project. Please confirm.

Is it mandaory to use the named ICs?

Klaus

 

[shirotpoison]

Hi,

this sounds like a school project. Please confirm.

Is it mandaory to use the named ICs?

Klaus

its a project for educational proposes , it's not a homework and whey you are asking if it was a schoolwork

 

[barry]

i did counted the u5 with the and gate , it hits 1 when 40 seconds , so what the values of RC do you suggest

Well, that's not what your schematic shows.Why should we believe the rest of your schematic? The way it's shown, it should count to 60; if it's only counting to 40, maybe you're missing a connection....

I would recommend NO RC.

 

[shirotpoison]

Well, that's not what your schematic shows.Why should we believe the rest of your schematic? The way it's shown, it should count to 60; if it's only counting to 40, maybe you're missing a connection....

I would recommend NO RC.

when i remove the RC it count till 40 sec , and didn't know where to connect the munits counter so i let it unconnected , when i cunnect bfor the RC the 40 sec problem show up , and when i connect after it doesn't count at all (munits block) if you dont believe my schematic you do this sumolation on proteus if care to help me becouse i realy did aplly this schematic and the RC really fix the problem of 40 sec in the seconds bloc

 

[KlausST]

whey you are asking if it was a schoolwork

I ask, because if it is for learning ... we should not give you a ready made solution.

A school project ist menat that you test it on your own. See that something goes wrong. You should learn how to find out what and why it´s goning wrong.
You should learn how to rectify these problems.

Sadly you did not answer my question about mandatory IC type.

Now I guess it was mandatory to use these devices. Because they want to generate these problems.
Using synchronous counters with clock_ENABLE don´t suffer from these problems.
Thus the industry use these syncronous solutions.

But using a synchronous system as a scool project ... means you don´t get problems, you don´t need to analyze anything, you don´t learn anything.

Klaus

 

[barry]

when i remove the RC it count till 40 sec , and didn't know where to connect the munits counter so i let it unconnected , when i cunnect bfor the RC the 40 sec problem show up , and when i connect after it doesn't count at all (munits block) if you dont believe my schematic you do this sumolation on proteus if care to help me becouse i realy did aplly this schematic and the RC really fix the problem of 40 sec in the seconds bloc

The major problem, as Klaus alluded to, is that this is an asynchronous design. As soon as the counter outputs reach 0110, the reset gets asserted. This forces the outputs to NOT be 0100. This is a classic race condition. I assume you were trying to solve this with the RC.

But i’m still confused as to why this only counts to 0100 and not 0110. I don’t know Proteus, but i assume you can look at the counter outputs, and AND gate output? You should do that.

 

[Aussie Susan]

Why not use a divide by 6 chip for the higher digit?
Thats. what I did back in the '70s and it worked perfectly
Susan

 

[barry]

I think that's what OP is trying to do.

Why not use a divide by 6 chip for the higher digit?

 

[shirotpoison]

Why not use a divide by 6 chip for the higher digit?
Thats. what I did back in the '70s and it worked perfectly
Susan

can you explain this more

--- Updated Mar 26, 2024 ---

I ask, because if it is for learning ... we should not give you a ready made solution.

A school project ist menat that you test it on your own. See that something goes wrong. You should learn how to find out what and why it´s goning wrong.
You should learn how to rectify these problems.

Sadly you did not answer my question about mandatory IC type.

Now I guess it was mandatory to use these devices. Because they want to generate these problems.
Using synchronous counters with clock_ENABLE don´t suffer from these problems.
Thus the industry use these syncronous solutions.

But using a synchronous system as a scool project ... means you don´t get problems, you don´t need to analyze anything, you don´t learn anything.

Klaus

the ic's type is LS74A192 and LS74A47

--- Updated Mar 26, 2024 ---

The major problem, as Klaus alluded to, is that this is an asynchronous design. As soon as the counter outputs reach 0110, the reset gets asserted. This forces the outputs to NOT be 0100. This is a classic race condition. I assume you were trying to solve this with the RC.

But i’m still confused as to why this only counts to 0100 and not 0110. I don’t know Proteus, but i assume you can look at the counter outputs, and AND gate output? You should do that.

the RC help solving the race glitch in the AND gate ,and the counter output are correct until i add the AND gate , then probleme start

 

[KlausST]

the ic's type is LS74A192 and LS74A47

The question was not about IC numbers (we already know), the question was about "mandatory or not".
Btw: the given IC numbers don´t exist.

Klaus

 

[shirotpoison]

The question was not about IC numbers (we already know), the question was about "mandatory or not".
Btw: the given IC numbers don´t exist.

Klaus

yes it's mandatory

 

[barry]

can you explain this more

--- Updated Mar 26, 2024 ---

the ic's type is LS74A192 and LS74A47

--- Updated Mar 26, 2024 ---

the RC help solving the race glitch in the AND gate ,and the counter output are correct until i add the AND gate , then probleme start

Again, why don't you look at the counter outputs and the AND gate signals?

And, you're not making a lot of sense. How could the counter output be correct without the AND gate? How could you say the RC solved the glitch when you say the counter isn't working after you add the AND gate?

 

[shirotpoison]

Again, why don't you look at the counter outputs and the AND gate signals?

And, you're not making a lot of sense. How could the counter output be correct without the AND gate? How could you say the RC solved the glitch when you say the counter isn't working after you add the AND gate?

i dont know the and gate jest glitch this all i know