Overclocking and X propagation in modelsim timing simulation

Status
Not open for further replies.

sprrenga

Newbie level 2
Joined
Jul 4, 2012
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,292
Hello,

When I overclock the timing simulation of a synthesized netlist along with .sdf file in modelsim, will the failing critial paths of the design propagate X ?
 

This is a very complex question. The simple answer is that is it better to rely on static timing analysis tools to determine your critical paths - they are far more accurate.

In dynamic simulation, you need assurance that all the models can accurately generate X's when there is a timing failure, and that the same models are written to accurately pass along the X's to an observable output. Typically, RTL simulation is overly optimistic, and gate-level simulation is overly pessimistic. The problem is further complicated by the fact that a post-synthesis netlist is a combination of both. (i.e. mostly gates, with memories and some mega-cells still modeled at the RTL level)
 

Status
Not open for further replies.
Cookies are required to use this site. You must accept them to continue using the site. Learn more…