Overclocking and X propagation in modelsim timing simulation

[sprrenga]

Hello,

When I overclock the timing simulation of a synthesized netlist along with .sdf file in modelsim, will the failing critial paths of the design propagate X ?

 

[dave_59]

This is a very complex question. The simple answer is that is it better to rely on static timing analysis tools to determine your critical paths - they are far more accurate.

In dynamic simulation, you need assurance that all the models can accurately generate X's when there is a timing failure, and that the same models are written to accurately pass along the X's to an observable output. Typically, RTL simulation is overly optimistic, and gate-level simulation is overly pessimistic. The problem is further complicated by the fact that a post-synthesis netlist is a combination of both. (i.e. mostly gates, with memories and some mega-cells still modeled at the RTL level)