dhasmana
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output buffer design
Hello,
How can be a buffer designed for 2.5GHz VCO (pure CMOS).I guess a gain of 10-15 should be fine @2.5GHz.
We tried diffamp structure , first stage differential to diferential and second stage differential to single ended (with 1pF of Fanout Capacitance) (this architecture is mentioned in SUN's thesis for VCO design) but getting a UGB (required UGB would be 12.5GHz assuming 2 pole response) seems not possible with the architecture used by us.Please comment in this regard.
Regards,
Jitendra Dhasmana.
Hello,
How can be a buffer designed for 2.5GHz VCO (pure CMOS).I guess a gain of 10-15 should be fine @2.5GHz.
We tried diffamp structure , first stage differential to diferential and second stage differential to single ended (with 1pF of Fanout Capacitance) (this architecture is mentioned in SUN's thesis for VCO design) but getting a UGB (required UGB would be 12.5GHz assuming 2 pole response) seems not possible with the architecture used by us.Please comment in this regard.
Regards,
Jitendra Dhasmana.