Output Buffer design for 5GHz VCO in pure CMOS

[dhasmana]

output buffer design

Hello,

How can be a buffer designed for 2.5GHz VCO (pure CMOS).I guess a gain of 10-15 should be fine @2.5GHz.

We tried diffamp structure , first stage differential to diferential and second stage differential to single ended (with 1pF of Fanout Capacitance) (this architecture is mentioned in SUN's thesis for VCO design) but getting a UGB (required UGB would be 12.5GHz assuming 2 pole response) seems not possible with the architecture used by us.Please comment in this regard.

Regards,
Jitendra Dhasmana.

 

[du_hast]

cmos vco design thesis

Hi,
Did you get an answer to your question? Currently im trying to design a buffer for my vco and i didnt find good information about it...any comments?

 

[mengcy]

vco buffer design

when I encounter this problem several months ago I can't find the answer,either.
At last we decide to translate the output of the VCO to square wave by series of inverter.
Because we care about the frequency of the VCO most.