Simply put,it's because nothing can happen in 0 second. Flipping the data in master latch doesn't happen in 0 second either, and if the current source to the master latch gets cut off while the master latch is about to be flipped, only current source is a weak feedback inverter in the master latch and it's up to the master latch whether it gets a new value or retain the old value.
Look at the transistor level circuit of a flop and look closely at the electrical aspect of how the master latch is flipped.
negative setup/hold are nothing special. it's just up to the timing relationship between the data path and clock path in a flop and how fast the master latch can flip.