Origin of Setup and hold time in Flip Flops ???

[raditsme]

Hello All,

Can anyone tell clearly, what is the origin of Setup and Hold time concepts in Flip-Flops. Please clarify with basic concepts .

I know the general Definition like:

Setup time. . . . . . . . . .the interval before the clock where the data must not change.
Hold time . . . . . . . . . the interval after the clock where the data must not change.

one can also say that violation of these times will lead to corrupted o/p.

but again the question is same...what is the origin of Setup and Hold time concepts in Flip-Flops.??

Please explain the negative setup and hold time concepts also?

 

[lostinxlation]

Simply put,it's because nothing can happen in 0 second. Flipping the data in master latch doesn't happen in 0 second either, and if the current source to the master latch gets cut off while the master latch is about to be flipped, only current source is a weak feedback inverter in the master latch and it's up to the master latch whether it gets a new value or retain the old value.
Look at the transistor level circuit of a flop and look closely at the electrical aspect of how the master latch is flipped.

negative setup/hold are nothing special. it's just up to the timing relationship between the data path and clock path in a flop and how fast the master latch can flip.

 

[yadavvlsi]

There is some input capacitance. So always some time is required to charge and discharge this capacitance.
For negative setup and hold time see this post https://www.edaboard.com/threads/7046/#17

 

[raditsme]

@lostinxlation , can u please elaborate your answer with transistor level figure of flip- flop??