Hi,
Please let me know , what will be the optimized verilog code of below:-
Code Verilog - [expand ] 1
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reg [ 31 : 0 ] control_pin_ton_delay_cntr;
always @ ( posedge clk_i or negedge nrst_i)
begin
if ( ! nrst_i)
control_pin_ton_delay_cntr <= 3 3'd0 ;
else if ( enable_i)
begin
if ( control_on_i)
control_pin_ton_delay_cntr <= 3 3'd1 ;
else if ( ( control_pin_ton_delay_cntr >= 3 3'd1 ) && ( control_pin_ton_delay_cntr < 3 3'h1FFFFFFFF ) && ( ~ iVOUT_UV_FAULT_LIMIT_UNMASK) )
control_pin_ton_delay_cntr <= control_pin_ton_delay_cntr + 3 3'd1 ;
else if ( control_pin_ton_delay_cntr == 3 3'h1FFFFFFFF )
control_pin_ton_delay_cntr <= 3 3'd0 ;
end
end
Last edited by a moderator: Jul 3, 2015