Optimized verilog code

[kannan_mahalingam]

Hi,

Please let me know , what will be the optimized verilog code of below:-

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Code Verilog - [expand]
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reg [31:0] control_pin_ton_delay_cntr; 
always @ (posedge clk_i or negedge nrst_i)              
begin
  if (!nrst_i)
       control_pin_ton_delay_cntr <= 33'd0;
  else if (enable_i)
  begin
    if (control_on_i)
        control_pin_ton_delay_cntr <= 33'd1;
else if ((control_pin_ton_delay_cntr >= 33'd1) && (control_pin_ton_delay_cntr <         33'h1FFFFFFFF) && (~ iVOUT_UV_FAULT_LIMIT_UNMASK))
         control_pin_ton_delay_cntr <= control_pin_ton_delay_cntr + 33'd1;
else if (control_pin_ton_delay_cntr == 33'h1FFFFFFFF)
       control_pin_ton_delay_cntr <= 33'd0;
  end
end

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[sharath666]

You can make the 3rd "else if" statement the 2nd one and shift the 2nd one to the 3rd one. In the 2nd "else if" statement, remove the check for cntr>=1 and cntr <1FFF*.