madhouse
Newbie level 5

I need to re-design an existing circuit to seriously reduce chip count and implement some new functions. The existing design is all in standard 74HC series logic. I'm looking at the possibility of experimenting with CPLD or FPGA as a solution, but I'm limited by the fact I can only realistically work with DIP / PLCC packages and home brew boards.
I've tentatively looked at the Xilinx Webpack, basically because I can easily throw together a JTAG programmer, can source XC9500 parts relatively cheaply, and in suitable packaging.
BUT - and the big one - I can't find any decent tutorials on the software. I'd prefer to use schematic design, as it's probably easier for me to grasp initially, and I'll worry about programming languages later.
Also, I'm open to suggestions on alternative devices to use - there is no particular reason for my initial choice other than it "seems to fit the bill".
BTW, I need to produce a dual port 2MByte SRAM, (one port write only, one port read only with a 21 bit counter generating the read address, and an external SRAM obviously). The write-only port needs a minimum cycle time of 200ns, the 2M SRAM has an access time of 70nS and the read-only port can latch data as soon as. There will be an external clock source for the counter, and the ability to either pre-load the counter or add an offset would be an advantage, but not essential. SRAM data does not necessarily need to be passed via the device.
In conventional TTL logic it's relatively simple, but with a high chip count, and lots of associated nasties....
Any suggetions on routes to take, tutorials, practical devices etc would be really good!
I've tentatively looked at the Xilinx Webpack, basically because I can easily throw together a JTAG programmer, can source XC9500 parts relatively cheaply, and in suitable packaging.
BUT - and the big one - I can't find any decent tutorials on the software. I'd prefer to use schematic design, as it's probably easier for me to grasp initially, and I'll worry about programming languages later.
Also, I'm open to suggestions on alternative devices to use - there is no particular reason for my initial choice other than it "seems to fit the bill".
BTW, I need to produce a dual port 2MByte SRAM, (one port write only, one port read only with a 21 bit counter generating the read address, and an external SRAM obviously). The write-only port needs a minimum cycle time of 200ns, the 2M SRAM has an access time of 70nS and the read-only port can latch data as soon as. There will be an external clock source for the counter, and the ability to either pre-load the counter or add an offset would be an advantage, but not essential. SRAM data does not necessarily need to be passed via the device.
In conventional TTL logic it's relatively simple, but with a high chip count, and lots of associated nasties....
Any suggetions on routes to take, tutorials, practical devices etc would be really good!