AllenD
Member level 5
Hi Everyone
I am laying-out a clocked circuit with TSMC 65 nm PDK. I noticed there are np layer (n+ S/D iron implantation) and pp layer(p+ ion implantation ). And I have heard that for the layout of a series connected inverters, for example, it's better to layout all the PMOS in a big nwell by connecting all the small nwells together.
My question is as follow:
1. Should I try to make a big np/pp drawing to connect all the np/pp from each small inverters together?
2. The nmos is layout in the np layer but its body contact is layout in pp drawing. Same for pmos, which is layout in pp drawing but the body contact is in np drawing. (because it is a contact used to bias a P-type substrate(Psub) )
Is there any pros or cons if the np drawing of a nmos (source/drain ion implantation) is connect to the np drawing of the pmos's bulk connect?
Thanks
Allen
I am laying-out a clocked circuit with TSMC 65 nm PDK. I noticed there are np layer (n+ S/D iron implantation) and pp layer(p+ ion implantation ). And I have heard that for the layout of a series connected inverters, for example, it's better to layout all the PMOS in a big nwell by connecting all the small nwells together.
My question is as follow:
1. Should I try to make a big np/pp drawing to connect all the np/pp from each small inverters together?
2. The nmos is layout in the np layer but its body contact is layout in pp drawing. Same for pmos, which is layout in pp drawing but the body contact is in np drawing. (because it is a contact used to bias a P-type substrate(Psub) )
Is there any pros or cons if the np drawing of a nmos (source/drain ion implantation) is connect to the np drawing of the pmos's bulk connect?
Thanks
Allen