Non-sequential timing problem in DC

[hayoula]

Hi,
How can I define timing constraints for non-sequential timing checks in Design Compiler?
For example two pins of a library module need this timing:
After a rising edge on pin A Pin B must remain high for a minimum of 100ns.
How can I set such a timing constraint in Design Compiler?
Can anyone help?

 

[tariq786]

You can code that as an assertion in systemverilog. But it will not be synthesized. Read page 4 from the following.

https://www.sutherland-hdl.com/papers/2006-SNUG-SanJose_SVA_for_designers_paper.pdf

 

[hayoula]

Hi tariq786,
That's not the case that I need. Maybe my explanation was not enough, I will try to make it much more clear:
The library module enforces DC to check this timing. I want to tell DC that in my design the real timing between the two signals which reach these pins is something more than minimum needed value, e.g. 150ns, and DC doesn't make a violation.
How can I do that?

 

[Kaisia]

just add one more constraint set_data_check

 

[hayoula]

Hi Kaisia,
Data-check is used when you want to tell DC check a timing between the two pins of a cell. This check already exists in the library of cell.
But I want to tell the dc that the real timing between the two signals which reach these pins are so a certain value and I want DC checks based on this value not the value calculated from paths which these signals are their endpoints.
Is there a solution?

 

[ljwfred]

virtual clock

 

[hayoula]

Hi ljwfred,
unfortunately that's not the case either. Virtual clock can be used when you have a path between the signals arriving at two pins and If it was the case I could also use multi-cycle path.
But there is no path between the 2 signals.
Is there any other sugggestion?

 

[ljwfred]

Hi, hayoula

did you mean you wanna scale library cells for synthesis?
or just a new designed cell is going to be used for synthesis.

 

[hayoula]

To ljwfred:
Neither , I just have a special cell which is provided to me as a single-cell library (DB and LIB files). This cell is non-sequential and has some data-checks between its pin. I have a controller that controls the timing of the signals which arrives at the pins of this cell.
For example this controller makes signal connected to pin A high and after 100 clock cycle it makes pin B low. So timing is OK but DC thinks of two signals changing at the same clock cycle and so timing is violated.
How can I tell him that it is OK and there is a real gap of 100 cycles between changes of two signals?

PS: There is no path between two signals and so multi-cycle path cannot be used either.

 

[tariq786]

If it is non sequential, then try not putting any timing constraint and see the synthesis result. Post your synthesis script and errors here.

 

[hayoula]

Hi tariq786,

If I remove constraints, there is no violations of course. So what should I send you?

 

[tariq786]

If there are no violations, go ahead and simulate the post synthesis netlist to see if it matches the pre synthesis netlist.

I am curious to look at your synthesis script. So you may post it here if you want.

 

[hayoula]

Thanks for following up tariq786,
Here is part of my script:

...
create_clock -name clock -period $CLK_PERIOD -waveform [list $CLK_PRD_HALF $CLK_PERIOD] CLK

set timing_enable_non_sequential_checks true

compile -map_effort high -area_effort high -ungroup
...

CLK is the clock who is connected to the clock of the controller and the controller generates needed signals for non-sequential object with data-check (as I mentioned before).

Regards,
Hayoula

 

[beowulf]

DC has a check 'set_data_check' which can be used to specify timing relation between two pins none of which is a clock.
One pin is the constrained (like data pin) and the other is relative (like a clock pin).
From your description,(... After a rising edge on pin A Pin B must remain high for a minimum of 100ns...) Pin_A is relative pin and Pin_B is the data pin
This path can be constrained as:
set_data_check -from Pin_A -to Pin_B -hold 100

You can get more information on this check from DC user guide or from the book "STA for nanometer designs"

Opinions/alternatives to this are welcome...

Beo

 

[hayoula]

Hi Beo,
I don't want to constraint. The constraint already exists. I want to inform DC about what my controller does for signals arriving at the pins, so it doesn't violate.
Refer to posts #5 and #9 please.