no. of stages in synchronizer v/s metastability

[suprio]

Synchronizers are basically extra flops added between the two clock domains to minimize the metastability.
For the same probability of failure due to metastability, is the no. of such flops dependent on the clock frequency? Or irrespective of the frequency of operation, the same no. of synchronizers will have the same probability of failure?

Seeking your invaluable response, soon!

Cheers,
Suprio

 

[koggestone]

basically 2 flops ( Independent of Frequency).

since as frequency changes , even rise/fall slopes of signal changes ( and also delays change as we move to faster process) to adjust the failure probability.

 

[rfsystem]

The key point is the definition of the failure.

If typical defined that there is a probability that the logic output is in the forbidden region is not the situation that lead to a logical error. It depend on further logical processing. If you only evaluate the polarity there is some more gain which reduce the risk of getting a failure. So you have to lok exactly of the definition of a logical error. Not only that the analog level is in forbidden reagion.