nmos bulk in cadence layout

[erikl]

I receive the "no stamped connection" error only when extracting the layout then do DRC. Before extraction there is no DRC error.

Khaled,
you are not expected to run a DRC on extracted layout; this will never work, because the extracted layout doesn't contain the necessary layers. If your DRC on the layout before extraction is ok, all is fine!

 

[gharuda]

In your layout why the transistor are in different orientation

use only (horizontal) or use only (vertical).

avoid using both.

 

[khaled2k]

I receive the "no stamped connection" error only when extracting the layout then do DRC. Before extraction there is no DRC error.

Khaled,
you are not expected to run a DRC on extracted layout; this will never work, because the extracted layout doesn't contain the necessary layers. If your DRC on the layout before extraction is ok, all is fine!

Hi erikl,
I didn't explain what I do well.
I run DRC then it is fine
Extract
run DRC on LAYOUT again, I receive no stamped connection error.

I do LVS I got 5 nets in EXTRACTED and 4 nets in SCHEMATICS, there is a strange node called 5, and there is no VDD in extracted view. check the previous log.

 

[pit1000]

Check contact to nwell. Maybe instead of N-type you have inserted contact P-type.

 

[jagvir]

Dear friends we can remove the error of "no stamped connection " in this way.
while drawing the schematic and filling the form of nmos or pmos make sure whether u had entered
body tie type (is in the form while entering width and length) ;- as integrated or detached.
integrated means in vxl bulk will be attached to source.
detached means in vxl bulk will be separate from source.
i hope the information provided will be enough