nmos bulk in cadence layout

[macg84]

nmos layout

Hallo and help me please...
i have to make a layout of two stage amplifier and i use technology -TECH_C35B4- but i have some problem because when i go to extract the schematic from my layout i get the same problems:

net_psub net_subtap:Causes multiple stamped connection
net_psub net_subtap:has multiple stamped connection

I have connect one nmos bulk to groun it is correct??? But i don't know why i get this error...helm me please

 

[AdvaRes]

cadence guard ring

Could you attach your schematic ?

 

[macg84]

ptap nmos

Is this that who you have required?

 

[erikl]

multiple stamped connection

Hallo and help me please...
...
net_psub net_subtap:Causes multiple stamped connection
net_psub net_subtap:has multiple stamped connection

I have connect one nmos bulk to ground, it is correct???

You must connect all your bulk taps to ground by metal,
and all your nwell taps to vdd by metal.

 

[macg84]

nmos bulk

Excuse me but the taps is the bulk contact in other words PD_C and ND_C??
or what else?

 

[macg84]

nmos layout bulk

is it true?

 

[AdvaRes]

nmos bulk layout

Look at this simple inverter layout:



PMOS bulk is connected to VDD using ptap, NMOS bulk is connected to gnd by ntap.

 

[erikl]

causes multiple stamped connections

Excuse me but the taps is the bulk contact in other words PD_C and ND_C?? or what else?

Bulk contacts for nfets on p-substrate (bulk), nwell contacts for pfets in nwell.

is it true?

- It seems that one plate of the cap is not completely connected to vdd by metal (piece of poly in between?)

- The guardRing around the cap (if it is a guardRing) seems to be not polarized. Must be connected to GND (if p-guardRing) or to VDD (if n-guardRing).

 

[macg84]

stamped connections from ptap

Yes your hypothesis is correct!!!! <<<<Thank you VERY MUCH>>>> It is the first time that I make a layout so I found much difficulties...Thanks a lot...
Considering that I am there i ask you an other doubt if the width oh poly or any material as the metal 1 is wider than the width of the contac (for example P1_C) do i have to use two contact?
To understand better my reasoning you can see the image...
Thanks

 

[erikl]

cadence nmos layout

If you have enough space, it's always better to have 2 contacts instead of one, at least for process sizes <= 0.18µm. By this, a better yield can be achieved. In many modern process technologies the usage of 2 contacts per connection is enforced by the design rules.

 

[macg84]

stamp error in cadence

Thanks for your very clear explanations... you are my hero

 

[fixrouter4400]

cadence guardring

Thanks for your very clear explanations... you are my hero

Did you managed to fix your STAMP ERROR problem?

Let us know so that people here can help you better.

Cheers

 

[macg84]

guardring pd_c

OK

 

[khaled2k]

Dear all,

I am new at layout. I have a simple inverter but have some errors when do LVS check. Please find the attached LVS log.
I also receive an error no stamped connection for the PMOS even substrate is connected (or I think so).
I did the VDD connection using ND_C and NWELL and GND using PD_C. Is this correct?

I realy got bored from this design. It has been ages since the stupid error of "no stamped connection" chasing me. Could anyone advise me?

 

[erikl]

I also receive an error no stamped connection for the PMOS even substrate is connected (or I think so).
I did the VDD connection using ND_C and NWELL and GND using PD_C. Is this correct?

I think this is correct. However your Diva LVS log-file tells you there is a node /5 which most probably should be connected to VDD. Find it and connect it to VDD. I can't see it on your layout plot, so I suppose there is another n-well in your layout which isn't connected to VDD. Just find this node /5 .

I realy got bored from this design. It has been ages since the stupid error of "no stamped connection" chasing me.

Of course we feel this is a stupid error, but it actually could show up an essential problem. Unfortunately nobody cares to give an easily understandable explanation for what this error message means: it simply means there is a well which is not connected (by metal!) to any potential (for an n-well mostly, but not necessarily VDD, for a p-well - if it exists - mostly, but not necessarily VSS or GND) - this results in the "no stamped connection" error message, or a well or the substrate is connected via (more than one) taps to different potential levels - this creates the error message "multiply stamped connection".

Pls. see also my posting above from Wed, 28 Jan 2009 16:45 , which seems to have helped the OP macg84. Good luck!

 

[khaled2k]

I also receive an error no stamped connection for the PMOS even substrate is connected (or I think so).
I did the VDD connection using ND_C and NWELL and GND using PD_C. Is this correct?

I think this is correct. However your Diva LVS log-file tells you there is a node /5 which most probably should be connected to VDD. Find it and connect it to VDD. I can't see it on your layout plot, so I suppose there is another n-well in your layout which isn't connected to VDD. Just find this node /5 .

I realy got bored from this design. It has been ages since the stupid error of "no stamped connection" chasing me.

Of course we feel this is a stupid error, but it actually could show up an essential problem. Unfortunately nobody cares to give an easily understandable explanation for what this error message means: it simply means there is a well which is not connected (by metal!) to any potential (for an n-well mostly, but not necessarily VDD, for a p-well - if it exists - mostly, but not necessarily VSS or GND) - this results in the "no stamped connection" error message, or a well or the substrate is connected via (more than one) taps to different potential levels - this creates the error message "multiply stamped connection".

Pls. see also my posting above from Wed, 28 Jan 2009 16:45 , which seems to have helped the OP macg84. Good luck!

Hi erikl,
Thank you for your interest. I did not create any pin called 5 in my layout, also I tried, search and did not find anything.
It is not clear to me which part is not connected to VDD? could you check the attached layout? if the poly intesects with the nwell, what should I do?
I am sorry but still can't understand where is the problem.

 

[AdvaRes]

Hi,
Correct the point that I mensonned in the figure and tell me what is the result.

 

[khaled2k]

Hi,
Correct the point that I mensonned in the figure and tell me what is the result.

Hi,

The two points (ND_C and PD_C) have the same x coordinates. They have the same distance to PMOS and NMOS respectively. I do not understand how to correct. Do you mean delete it or what?

Thanks in advance.

 

[AdvaRes]

Hi,
Correct the point that I mensonned in the figure and tell me what is the result.

Hi,

The two points (ND_C and PD_C) have the same x coordinates. They have the same distance to PMOS and NMOS respectively. I do not understand how to correct. Do you mean delete it or what?

Thanks in advance.

Try one of the following modification

 

[khaled2k]

Hi,
Correct the point that I mensonned in the figure and tell me what is the result.

Hi,

The two points (ND_C and PD_C) have the same x coordinates. They have the same distance to PMOS and NMOS respectively. I do not understand how to correct. Do you mean delete it or what?

Thanks in advance.

Try one of the following modification

Hi AdvaRes,
Unfortunately it didn't work. I receive the "no stamped connection" error only when extracting the layout then do DRC. Before extraction there is no DRC error.