negative time in post-synthesis simulation and post-layout simulation using Modelsim

[quiet83]

how can i do with the negative delay in the sdf file for post-synthesis or post-layout simulation?
Becuase Modelsim will make the negative value to zero, but I think it may be some hold time problem when the hold time is set to zero due to the negative value.

 

[asic_service]

There is a an option "+no_neg_tchk" in vsim. I suppose if you don't use this option, vsim will accept negative values.
Even if vsim will never accept negative values, I think the negative value is usually very small, and we usually have additional setup/hold timing margin at STA (note, this margin usually can't be simulated). So, if the hold margin >= | negative value in the SDF file | , then you can safely let vsim set it to 0.