negative propagation delay buffer

[asicengineer1]

negative delay buffer

Hi all,
I came across a suggestion saying that its possible to insert negative propagation delay buffers in the data paths which have timing violations. I'm not able to understand how its possible to have a buffer which speeds up. can someone explain about this ?

p.s : I'm not talking about introducing a flop to break the reg-to-reg path.

 

[abhikohli]

logic+delay+buffer

I don't think time travel is still possible (even for signals) so receiving a signal before sending it doesn't seems to much realistic to me (only than can a buffer make propagation time -ve) However, if we want to remove the propagation delay 'affect' for a ckt, delay buffer can be inserted in clock path which will delay clk = data propagation delay or more and hence data path slack will become +ve.
Just an idea. Open to comments from others.

 

[pratap_v]

negative propagation delay

As u said a buffer includes the delay, but as we know that in latest technologies the delay is mainly caused from the nets. The propogation of a voltage step along a wire is t(delay) = kx(square).
if the net is made half ,then overall delay trough net reduces and now insert a buffer with least propogaton delay. so the overall delay through that logic path is reduced.

 

[abhikohli]

propagation delay buffer

Yes thats true. Carefully chosen buffer drive etc will reduce net delay however still the total delay value will still be +ve.

 

[asicengineer1]

i think what pratap is suggesting makes sense. but, how different is this from breaking a long path by inserting buffers as it is done to reduce the reg-to-reg delay?

the first answer that kohli gave is skewing the clock or useful skew to remove violation,am i right ?

 

[abhikohli]

I'd rather say it as clk tree balancing. May be.

 

[arun_prabu]

It is true negative propagation delay can be achieved. I had heard about negative propagation delay inverters. Suppose if the consider any voltage below 20% of VDD as logic 0, and if the input changes from logic 0 to logic 1, in a negative prop delay inverter, the output goes to logic 0 before input changes to logic 1 (i.e., as soon as the input crosses 20% of VDD and before reaching 80% of VDD). This kind of inverters have poor noise margin. I think same concept can be applied to buffers also.

 

[abhikohli]

Poor noise margin ?? At 20% ,That would be no noise margin. In designs where SI is causing so much concerns these days, I don't know how these 'low' noise margin buffers will perform ? (I know I'll b raising many eyebrows here, where the hell did SI came into picture ?? We are talking abt propagation delays u need to see data/eye-diagram on scopes (NOT L-analyzers) to believe me.) Though many design do make use of this tech. with careful noise/delay trade-off.(Xilinx says (I don't recall exactly where) there switch matrix are not just passive interconnects, they are active line drivers to reduce delay) However here it more of signal conditioning where delay is reduced by improving a deteriorating rise/fall time.
@asicengineer1 Yes my first rply is 'useful skew to remove violation' sorry for not reading ur post properly.

 

[vinayakbhat82]

As I understand, propagation delay is measured at 50% of input and output levels i.e. the time difference between input reaching its 50% and output reaching 50%. Hence, if output reaches its 50% before input has reached its 50%, then we have a scenario of a negative propagation delay. It has nothing to do with 20% (or any other %) of VDD. Please disagree with reasons if you feel otherwise.

 

[onlymusic16]

Poor noise margin ?? At 20% ,That would be no noise margin. In designs where SI is causing so much concerns these days, I don't know how these 'low' noise margin buffers will perform ? (I know I'll b raising many eyebrows here, where the hell did SI came into picture ?? We are talking abt propagation delays u need to see data/eye-diagram on scopes (NOT L-analyzers) to believe me.) Though many design do make use of this tech. with careful noise/delay trade-off.(Xilinx says (I don't recall exactly where) there switch matrix are not just passive interconnects, they are active line drivers to reduce delay) However here it more of signal conditioning where delay is reduced by improving a deteriorating rise/fall time.
@asicengineer1 Yes my first rply is 'useful skew to remove violation' sorry for not reading ur post properly.

I agree with arun_prabhu.. Yes it can be achieved. The cons is that your inverter/buffer will be skewed(p/n would not be ~2:1) hence poor noise margin. Proper SI analysis should be done in that case.