Poor noise margin ?? At 20% ,That would be no noise margin. In designs where SI is causing so much concerns these days, I don't know how these 'low' noise margin buffers will perform ? (I know I'll b raising many eyebrows here, where the hell did SI came into picture ?? We are talking abt propagation delays
u need to see data/eye-diagram on scopes (NOT L-analyzers) to believe me.) Though many design do make use of this tech. with careful noise/delay trade-off.(Xilinx says (I don't recall exactly where) there switch matrix are not just passive interconnects, they are active line drivers to reduce delay) However here it more of signal conditioning where delay is reduced by improving a deteriorating rise/fall time.
@asicengineer1 Yes my first rply is 'useful skew to remove violation' sorry for not reading ur post properly.