negative delay in report_timing

[snehal.saini]

I see negative delays for few cells in the report_timing report. What does this indicate? this delay has been subtracted in the path delay. is this correct? if yes, why? can anyone please explain?

 

[oratie]

The delay for each cells is characterized from 50% of input pin transition to 50% of output transition (usually). So, if input transition is long and the output transition is short, the delay will be negative. It may happens, when the drive strength of these cells are high and output capacitance of them are low (so, output transition is very short).

 

[snehal.saini]

ok.. thank you... but can the output change before 50% of input pin transition?

 

[oratie]

Yes, it happens. In spice simulation you will see it.

 

[yadavvlsi]

can the output change before 50% of input pin transition?

Yes, this can happen in tightly packed layouts due to effect of cross-talk. If output node is surrounded by high drive strength aggressor than output node is charged due to the transition on the aggressor. I think you seeing the negative delay after postroute stage when timing is SI enabled.