negative cap values in mos
Hi Sunjiao/ Vamsi,
Interesting discussion here. My thoughts on this :
the main point you have to understand is that the concept shown in the pdf file works on the principle of partial positive feedback (to ensure that it is an amplifier and not an oscillator).
To get signs right, let me denote my conventions :
Vinp - positive input terminal of opamp
Vinn - negative input terminal of opamp
Voutp - positive output terminal of opamp
Voutn - negative output terminal of opamp
Capacitors Cf and Cf' are connected in postive feedback configuration, ie, Cf connects Vinn to Voutn and Cf' connects Vinp to Voutp. At high frequencies, if you consider the capacitive impedance as short, then you have a positive feedback loop, if this loop gain >1, you have an oscillator
For this to work properly, you have to use partial positive feedback, loop gain <1 - this is according to my understanding.
This concept of bandwidth enhancement is not new - it is also called neutralization in literature. The main idea is to cancel the effect of Cgd - feedforward gate to drain capacitance. This Cgd is harmful because it creates a right half plane zero (which causes negative phase shift) and you need to push the dominant pole lower for stability reasons which reduces the bandwidth. Cgd is in a feedforward path which has opposite phase shift (180 deg phase shift in the forward path) as compare dto the original direct path. Whenever a feedforward path has opposite phase shift - you get a right half plane zero (RHP), but if the phase shift is same, you get a left half plane (LHP) zero.
LHP zero is beneficial because it creates positive phase shift.
If you connect an equivalent capacitor (similar in value to Cgd) at opposite terminals, then you have a LHP zero now, which negates the effect of RHP zero of Cgd. Now, you don't have to push the dominant pole lower, which helps in "increased bandwidth" because you don't have to worry about the effects of the RHP zero.
Now, maybe Sunijao can explain the behavior of this circuit for specific values of feedforward and Cgd capacitance used.
By definition, capacitance terminals do not have any explicit polarity - except for cases like diode capacitance where you need reverse bias etc, so I don't understand the negative and positive terminals of capacitance here.
You can also think about this circuit as inductor peaking circuit. The partial positive feedback creates a negative capacitance at the input. Capactive impedance is -1/jwC. Now, if you write -1 as j², then you end up with j/wc. or you have an effective inductor of value
(1/w*w*C) - the input impedance is inductive. Inductive peaking is usually used for bandwidth enhancement - another way of looking at this configuration.
Hope to continue this discussion...
Bharath