negative CMOS capaticance

[sunjiao3]

cmos negative capacitance

Dear all, I am trying to get 2 negative capacitances used in differential pairs to enlarge its bandwidth. I use the gate of a NMOS transistor as the "positive" end and, connect the drain and source of it as the "negative" end. I found 2 strange things.
First, the bandwidth is decreased rather than increased. The smaller the size of MOS cap, the smaller the loss of bandwidth would be.
Second, if I invert the connection of this MOS cap, I mean, connect the "positive" end to Vout2 and "negtive" end to Vin1, the loss of bandwidth is also decreased.
Could any of you please give me a clear explanation of these 2 problems?
Thank you in advance.

 

[Vamsi Mocherla]

negative cmos capacitance

Dear Sunjiao,

I do not understand how do you realize a negative capacitance by connecting the negative terminal of the cap. As far I know, whether you connect the gate or the source+drain connection, it is the same capacitance you are realizing. Only you are realizing a bottom plate connection.

 

[sunjiao3]

capaticance

Dear Vamsi Mocherla, the negtive MOS capacitance is realized in this way in the attached file1. In fact, it is formed by negtive miller capacitance. And I use MOS cap here to replace the normal cap. Like what a paper used in attached file2.

To my disappointment, it doesn't increase the bandwidth at all. What's worse, it decrese it.

I don't know why.

And, you mean that the positve end and negative and of MOS cap can be altered freely, right?

 

[Vamsi Mocherla]

rhp zero effect

Dear Sunjiao,

Well, due to miller effect, if there is a cap across an amplifying stage, the efective cap seen at the input and the output will be C*(1- Av) and C*(1-1/Av) respectively. Hence a negative capacitance can be realized. Makes sense here. Hence the negative capacitance at the input will try to cancel the gate-source capacitance and hence yielding a better frequency response. On the load side, the capacitor would still short at higher frequencies. Only when Av becomes less than one, then you will see some improvement in the load capacitance, while at the gate, the capacitance becomes positive.

Coming to the positive end and the negative end of the cap, it should not matter which end of the cap you connect. What matters is the amount of charge stored in the capacitor. One important thing you should note is whether you have given the bias voltage which operates the MOScap in its linear region. So, please make sure of that.

I hope that it helps

 

[tsb_nph]

negative cap values in mos

Hi Sunjiao/ Vamsi,
Interesting discussion here. My thoughts on this :

the main point you have to understand is that the concept shown in the pdf file works on the principle of partial positive feedback (to ensure that it is an amplifier and not an oscillator).

To get signs right, let me denote my conventions :
Vinp - positive input terminal of opamp
Vinn - negative input terminal of opamp
Voutp - positive output terminal of opamp
Voutn - negative output terminal of opamp

Capacitors Cf and Cf' are connected in postive feedback configuration, ie, Cf connects Vinn to Voutn and Cf' connects Vinp to Voutp. At high frequencies, if you consider the capacitive impedance as short, then you have a positive feedback loop, if this loop gain >1, you have an oscillator For this to work properly, you have to use partial positive feedback, loop gain <1 - this is according to my understanding.

This concept of bandwidth enhancement is not new - it is also called neutralization in literature. The main idea is to cancel the effect of Cgd - feedforward gate to drain capacitance. This Cgd is harmful because it creates a right half plane zero (which causes negative phase shift) and you need to push the dominant pole lower for stability reasons which reduces the bandwidth. Cgd is in a feedforward path which has opposite phase shift (180 deg phase shift in the forward path) as compare dto the original direct path. Whenever a feedforward path has opposite phase shift - you get a right half plane zero (RHP), but if the phase shift is same, you get a left half plane (LHP) zero.
LHP zero is beneficial because it creates positive phase shift.
If you connect an equivalent capacitor (similar in value to Cgd) at opposite terminals, then you have a LHP zero now, which negates the effect of RHP zero of Cgd. Now, you don't have to push the dominant pole lower, which helps in "increased bandwidth" because you don't have to worry about the effects of the RHP zero.

Now, maybe Sunijao can explain the behavior of this circuit for specific values of feedforward and Cgd capacitance used.

By definition, capacitance terminals do not have any explicit polarity - except for cases like diode capacitance where you need reverse bias etc, so I don't understand the negative and positive terminals of capacitance here.

You can also think about this circuit as inductor peaking circuit. The partial positive feedback creates a negative capacitance at the input. Capactive impedance is -1/jwC. Now, if you write -1 as j², then you end up with j/wc. or you have an effective inductor of value
(1/w*w*C) - the input impedance is inductive. Inductive peaking is usually used for bandwidth enhancement - another way of looking at this configuration.

Hope to continue this discussion...

Bharath

 

[sunjiao3]

avoid miller capacitance in differential pair

Hi, friends, thank you all for your clear answers and patience. As for what I said about positive connected MOS CAP and negative connected MOS CAP, I will attach a graph here to illustrate it more clear.

In my opinion, the diffecent cap between the 2 connected cases is caused by their different biasing. In the attached file, The VAi is of cource higher than Vini, and the positive connected MOS cap is forward biased while it is backward biased in negative connected situation. And the Capacitance is different.

What troubles me most is that why the negative CAP used here doesn't enlarge the bandwidth as the theory promised? I used a true cap to repalce the MOS cap here, and the result is the same-----the bandwidth decreases rather than increases. Could anyone of you please enlight me on this issue?

Thank you in advance.

 

[aryajur]

cgd capacitance

tsb_nph has given a really nice explanation behind the working principle of this negative capacitance effect. 1 thing that I suspect that if its not increasing your bandwidth is that since the effective negative capacitance would cancel the capacitance at the gate nodes, maybe the capacitance of the gate nodes in your circuit is already too small to limit your bandwidth in the frequency response.
What you can try is maybe load your gates with a large capacitance so that the gate nodes become the dominant poles of your frequency response and then find the small signal gain from the input to the output. Then add the capacitors as shown in the PDF to make negative capacitances on the gate so that you know exactly by how much the capacitance should get cancelled and then see if your dominant poles move further. This would help to clear the concept and see if it is working as expected.
If it works like this we can go further and find out where exactly are the dominant poles of your circuit.

 

[Vamsi Mocherla]

negative capacitance mos + cgs

In the diagram sunjiao has shown, the gate nodes are not necessarily the dominant poles becuase they are being driven by a source followers. sunjiao has four of those kind of stages. The idea in cascaded stages is to avoid internal poles and also eliminate the right hand plane zeroes which give a negative phase response.

tsb, good points about the positive feedback. Points taken. But one small clarification, the capacitance at the gate of the input pairs forms the part of the feedback loop. Hence the loop gain has to be less then one for stable operation. So, A*(Cin/Cin+Cf) should be the loop gain, if I am not wrong where Cin is the input parasitic capacitance of the differential pairs. Hence we can think about the sizing of the Cf capacitor.

 

[sunjiao3]

phase shift right hand plane zero

Hello, friends. I've just tried the method aryajur suggested. I added a capacitance of about 200ff to the gate of each stage of differential amplifiers to decrease the total 3dB bandwidht from 642MHz to 554MHz. Then, I added the crossing MOS CAP again, the bandwidth dropped again.
Could any one of you please enlight me on this issue?

 

[tsb_nph]

cmos negative capacitance

Hello, friends. I've just tried the method aryajur suggested. I added a capacitance of about 200ff to the gate of each stage of differential amplifiers to decrease the total 3dB bandwidht from 642MHz to 554MHz. Then, I added the crossing MOS CAP again, the bandwidth dropped again.
Could any one of you please enlight me on this issue?

Hi sunjiao3,
To get to the bottom of this problem, I think it is better to look at a single stage amplifier to simplify the process rather than the cascaded amplifier. To identify the basic problem, simulate just a single stage differential amplifier without the source follower.

1) First compute DC gain and 3-dB frequency. The dominant pole is at the output (Rout*Cout). Calculate the value of Cgd, Cgs etc.

2) Put an ideal croos-coupled capacitor the same value, 25% lower, 50% lower, 25% higher and 50% higher than the value of Cgd you calculate in step (1). Now, note the gain and 3-dB in each of these five cases.

Please note that you perform bandwidth enhancement only if you move the 3-dB pole at the output in some way. Since you are not modifying Rout, you have to modify Cout in order to have an impact on the bandwidth (3-dB frequency)

Once you finish these simulations, please post your results.

I have uploaded a classic paper which discusses the basic concept of neutralization here :

 

[sunjiao3]

cgd cancellation inductor

Hello, friends, thank you all for your clear answers. I did the simulation as tsb_nph suggested. And here is the answer: The gain of each stage is about 15DB, and it remain unchanged. The value of Cgd is about 10ff, and here is the simulation result of single amplifier stage (no soure follower, no load)
the value of crossing cap
0 0.5Cgd 0.75Cgd 1Cgd 1.25Cgd 1.5Cgd
the 3db bandwidth of single stage (no load) /Hz
1.645G 1.542G 1.492G 1.445G 1.401G 1.360G
the 3db bandwidth of single stage (cascaded with same stage)/Hz
586M 651.5M 688.5M 728.1M 769.4M 811M
It can be found that the crossing cap only enlarge the bandwidth of a amplifier when it is cascaded with the other same stage.


And, as for the main pole's location. Vamsi Mocherla and aryajur are right, the main pole seems to be locaded in the input end of source follower. So, when I casecaded the same stages(no source follower used), and use the crossing caps, the bandwidth increases. And I am investigating into it.