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Need of Endcaps in design?

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cvnanil

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endcap decap well-tap

Can any one explain why do we end cap cells, while doing block level design??
 

Endcaps are needed to ensure that particular transistor will get fabricated properly.. If the endcap is not kept for the minimum value, then your souce & drain area may get shorted.. Thus your transistor will not work as you are expected.

Hope this helps.
 

I hope that u might be knowing what is DRC & its rules. The DRC check will ensure that all the shapes can be manufactured by keeping the minimum DRC rules. If its not, then the particular shape may not be manufactured as expected.

In 90nm, the M1 width & spacing is 0.12u. All M1 shapes should meet this requirement else the M1 shape may not be fabricated properly. If two M1 are running parallel to each other, these M1 are may get shorted if you didn't meet the DRC rules.

Similarly, there is minimum requirements for endcap also. If u look at the transistor layout, the PO is always extended to certain extent to meet the endcap DRC rule. If not, then your source & drain area may get short due to this endcap violation. Then the structure will not look like transistor since the gate is not properly fabricated.
 

What exactly an endcap cell conists of?? what makes it imporatant to place at ends. Is it free space we are leaving to satisfy DRC at the end of the rows or some thing else?
 

End cap is a cell and if it is not can anyone plz elaborate...
Please don't take the wrong concepts and put here which may arise confusion to all of us...
 

There is no End-Cap cell. I have never seen any end-cap cells in std cell Library.

Are you talking about Poly end-cap?.
 

No..I am just talking about the End cap cell which is there and it is given in the SOC User Guide given by the CADENCE and we have used in our project...and its a part of library component...

I request you to please check it out and let us know more about this....

Reply me
Bye take care

Added after 4 minutes:

There are few cells available like Filler Cells, Decap Cells, Well Tap Cell and one among them is End Cap cells...And we donno about End cap cells and Well tap cells...Wt is the purpose and why it is used....I request the people to do more research in this particular topics and kindly let us know so that it will be good for everyone who are begineers...


Reply me
Bye
 

I'm working in std cell lib development team... I have seen Filler, Decap, Delay, Well Tie, Tie Vdd, Tie Gnd & SRPG cells... I have never heard of End Cap cell..

Could you please upload that SOC user guide?, let me have a look...

If you want , I can upload Synopsys Library Compiler User Guide.. You can find all the kind of special cells defination there.
 

please discuss about endcap cells used at the stage of place and route.
 

hi kumar,,
i also confused with the discusion, convinced with the kumar explanation initially as it is near to theortical books, but also found end cap cells in the encounter user guide,,, i had attached the user guide,,,End cap cell information given in 432 page
 

I have no idea about End-Cap cells.. I will check it with my friends & will get back to you..
 

Hi ,

Endcap cells are inserted to fullfill well tie off specifications for the cell rows. Endcaps dont have signal connectivity. They only have connectivity to power and ground distribution in the design. Endcaps have a fixed attribute and cannot be moved by optimization steps. Endcaps are placed at the end of cell rows and handle end of row well tie off requirement.

Thanks
 
kumar_eee said:
I hope that u might be knowing what is DRC & its rules. The DRC check will ensure that all the shapes can be manufactured by keeping the minimum DRC rules. If its not, then the particular shape may not be manufactured as expected.

In 90nm, the M1 width & spacing is 0.12u. All M1 shapes should meet this requirement else the M1 shape may not be fabricated properly. If two M1 are running parallel to each other, these M1 are may get shorted if you didn't meet the DRC rules.

Similarly, there is minimum requirements for endcap also. If u look at the transistor layout, the PO is always extended to certain extent to meet the endcap DRC rule. If not, then your source & drain area may get short due to this endcap violation. Then the structure will not look like transistor since the gate is not properly fabricated.
Click to expand...

What is PO?
 

decaps r as a current source endcaps are a poly extension to avoid drain source short.

*caps is attached to these words just to mislead :idea: thinking both would do same job :!:
 

It's for latch up ! perhaps
 

Endcaps are added around the edge of digital core in triple well design, it's used to close the nwell of stdcells to form a ring, which encloses all the digital circuits, what I know is that it's used to speparate the core logic from the outside.
 

Re: endcap decap well-tap

cvnanil said:
Can any one explain why do we end cap cells, while doing block level design??
Click to expand...

As per SOC Encounter user guide, End-cap cells are preplaced physical-only cells required to meet certain design rules & placed at the ends of the site rows. In some technologies, they serve for power distribution as well.

But can someone please tell what exactly are these design rules ? :roll:
 

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