kumar_eee said:I hope that u might be knowing what is DRC & its rules. The DRC check will ensure that all the shapes can be manufactured by keeping the minimum DRC rules. If its not, then the particular shape may not be manufactured as expected.
In 90nm, the M1 width & spacing is 0.12u. All M1 shapes should meet this requirement else the M1 shape may not be fabricated properly. If two M1 are running parallel to each other, these M1 are may get shorted if you didn't meet the DRC rules.
Similarly, there is minimum requirements for endcap also. If u look at the transistor layout, the PO is always extended to certain extent to meet the endcap DRC rule. If not, then your source & drain area may get short due to this endcap violation. Then the structure will not look like transistor since the gate is not properly fabricated.
Can any one explain why do we end cap cells, while doing block level design??
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