Need help with syntax for replicator in Verilog

[Dasco]

I wanna replicate every bit of the input and write it all out
something like this :

---

Code Verilog - [expand]
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module (input, output);
    wire input [n+1: 0];
    parameter  M ; // replicating factor
    parameter n; // the width of the input
    wire output [M*(n+1) :0]; 
    integer i ;
        initial begin
              for(i = 0; i < n ; i = i + 1) 
    assign output [(n*M)+7: (n*M)]  = M {input[n]} ;
    end 
    endmodule

---

but I am missing the right syntax

any help??

thanks in advance!!

 

[sakthikumaran87]

replication can be done using {M{N}} =>NNNN(for M times). for ex {3{4}} -> 444

 

[FvM]

As an additional remark, the part select output [(n*M)+7: (n*M)] is no valid Verilog syntax. Either use a bit select with an additional bit iteration loop or indexed part select syntax as shown below. Refer to the Verilog specification or your preferred text book for details.

reg [15:0] big_vect;
reg [0:15] little_vect;

big_vect[lsb_base_expr +: width_expr]
little_vect[msb_base_expr +: width_expr]
big_vect[msb_base_expr -: width_expr]
little_vect[lsb_base_expr -: width_expr]

Furthermore, some variable width expressions in the example obviously need recalculation.

 

[Dasco]

As an additional remark, the part select output [(n*M)+7: (n*M)] is no valid Verilog syntax. Either use a bit select with an additional bit iteration loop or indexed part select syntax as shown below. Refer to the Verilog specification or your preferred text book for details.

reg [15:0] big_vect;
reg [0:15] little_vect;

big_vect[lsb_base_expr +: width_expr]
little_vect[msb_base_expr +: width_expr]
big_vect[msb_base_expr -: width_expr]
little_vect[lsb_base_expr -: width_expr]

Furthermore, some variable width expressions in the example obviously need recalculation.

that is exactly the obstacle
What I want to do is :
assign output [M*n : 0] = append (M*input[n], M*input[n-1]....................., M*input[0] )
how should i define this??

I know how to do it if i give M and N values but I do not know how to do it with parameters
where should i start??
thanks in advance

 

[FvM]

A simple construct that works with a minimum of special Verilog syntax

for(i = 0; i < n ; i = i + 1) 
  for(j = 0; j < M ; j = j + 1) 
    output[i*M+j] = input[i];

 

[Dasco]

A simple construct that works with a minimum of special Verilog syntax

for(i = 0; i < n ; i = i + 1) 
  for(j = 0; j < M ; j = j + 1) 
    output[i*M+j] = input[i];

so in my case it would be something like :

---

Code Verilog - [expand]
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module (input, output);
wire input [n+1: 0];
parameter M ; // replicating factor
parameter n; // the width of the input
wire output [M*(n+1) :0];
integer i, j ;
initial begin
 
for(i = 0; i < n ; i = i + 1) 
  for(j = 0; j < M ; j = j + 1) 
     = input[i];
assign  output[i*M+j] = M {input[i]} ;
end
endmodule

---

right?

i will try it and get back to you
thanks in advance

 

[FvM]

so in my case it would be something like

No, I meaned the code as is. Your's is involving various syntax errors.

As previously mentioned, the definitions of wire input and output should be corrected to give the inteded number of bits.

 

[Dasco]

No, I meaned the code as is. Your's is involving various syntax errors.

As previously mentioned, the definitions of wire input and output should be corrected to give the inteded number of bits.

what do you mean ?
should i use reg instead of wire??

 

[FvM]

Yes, or assign in a generate loop. Your tool will tell you about incorrect syntax.

 

[Dasco]

Yes, or assign in a generate loop. Your tool will tell you about incorrect syntax.

I did assign it in the 2d loop
i have to look into the generate thing
any example?
thanks

 

[FvM]

Same point as before: If you're not aware of the generate syntax, why don't you use a regular for loop with a reg variable. They all compile to the same gate level code.

 

[Dasco]

Same point as before: If you're not aware of the generate syntax, why don't you use a regular for loop with a reg variable. They all compile to the same gate level code.

something like this :

module (input, output);
reg input [n+1: 0];
parameter M ; // replicating factor
parameter n; // the width of the input
reg output [M*(n+1) :0];
integer i, j ;
initial begin
 
for(i = 0; i < n ; i = i + 1) 
  for(j = 0; j < M ; j = j + 1) 
     = input[i];
assign  output[i*M+j] = M {input[i]} ;
end
endmodule

am i right?