Dasco
Junior Member level 2
I wanna replicate every bit of the input and write it all out
something like this :
but I am missing the right syntax
any help??
thanks in advance!!
something like this :
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 module (input, output); wire input [n+1: 0]; parameter M ; // replicating factor parameter n; // the width of the input wire output [M*(n+1) :0]; integer i ; initial begin for(i = 0; i < n ; i = i + 1) assign output [(n*M)+7: (n*M)] = M {input[n]} ; end endmodule
but I am missing the right syntax
any help??
thanks in advance!!
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