As an additional remark, the part select
output [(n*M)+7: (n*M)] is no valid Verilog syntax. Either use a bit select with an additional bit iteration loop or indexed part select syntax as shown below. Refer to the Verilog specification or your preferred text book for details.
Code:
reg [15:0] big_vect;
reg [0:15] little_vect;
big_vect[lsb_base_expr +: width_expr]
little_vect[msb_base_expr +: width_expr]
big_vect[msb_base_expr -: width_expr]
little_vect[lsb_base_expr -: width_expr]
Furthermore, some variable width expressions in the example obviously need recalculation.