Need help with Nexys2 Digilent board 7segment display

[OhJ]

hello all,

I have a digilent nexys2 board, and was just trying out my hands on simple circuits.

Question: for ex: on a 3x8 decoder circuit, how do I control just one of 4-7segment displays on the board. In my present design, numbers show up on each of the 4-7SDs at the same time.

Please help me with info on to control each of the 7SDs one by one / individually.

regards
OhJ

 

[mrflibble]

You can see on the nexys2 schematic that the 7-segments + dot share common pins. There's also 4 anodes (or cathodes, I forget which variety this was). By driving just one of those at a time + driving the 7 segments you can selectively drive each segment seperately. Then you just scan across the segments fast enough so you don't see any flicker. Anything from 200 Hz - 1 kHz works just fine for that.

Hope that helps.

 

[BlackHelicopter]

OhJ, have a look at page 6 of this pdf for your board, It shows what mrflibble is describing.

**broken link removed**

Here's some code I wrote a while back for my Basys2 board. It uses a switch on the board to select between two values (x/y) and displays them on the 7seg LEDs. There are other ways to do what I did, so feel free to experiment.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity led_hex is
port ( 
      clk 		: in std_logic;
      reset_f 	: in std_logic;
      xy_sel	        : in std_logic;
      sseg_an0    : out std_logic;
      sseg_an1    : out std_logic;
      sseg_an2    : out std_logic;
      sseg_an3    : out std_logic;
      sseg_ca 	: out std_logic;
      sseg_cb 	: out std_logic;
      sseg_cc 	: out std_logic;
      sseg_cd 	: out std_logic;
      sseg_ce 	: out std_logic;
      sseg_cf 	: out std_logic;
      sseg_cg 	: out std_logic
	);
end led_hex;

architecture rtl of led_hex is

	
	signal sseg_anode 		: unsigned(1 downto 0);
	signal sseg_anode_data 	: std_logic_vector(3 downto 0);
	signal sseg_cathode 		: std_logic_vector(6 downto 0);
	signal sseg_data 		: std_logic_vector(3 downto 0);
	
	signal x_data 			: std_logic_vector(11 downto 0);
	signal y_data 			: std_logic_vector(11 downto 0);
	signal xy_data 			: std_logic_vector(11 downto 0);
	
begin	
	
	x_data <= x"3FE";  -- test data x
	y_data <= x"3FD";  -- test data y
	
	xy_data <= x_data when xy_sel = '0' else y_data;
	
	clk_prescaler: process (clk)
		variable cnt : integer range 0 to 20000; -- 20,000 ~= 1.67ms x 4 = refresh
	begin
		if clk'event and clk = '1' then
			if cnt = 20000 then -- counter prescaler
				cnt := 0;
			else
				cnt := cnt + 1;
			end if;
			if cnt = 20000 then -- sseg anode sel
				sseg_anode <= sseg_anode + 1;
			end if;
		end if;
	end process;
	
	sseg_enable: process (sseg_anode, xy_data)
	begin
		case sseg_anode is
			when "00" => -- disp 1
				sseg_anode_data <= "1111";  -- first sseg is turned off
				sseg_data <= xy_data(11 downto 8); --sseg_cath_data
			when "01" => -- disp 2
				sseg_anode_data <= "1101";
				sseg_data <= xy_data(11 downto 8);
			when "10" => -- disp 3
				sseg_anode_data <= "1011";
				sseg_data <= xy_data(7 downto 4);
			when "11" => -- disp 4
				sseg_anode_data <= "0111";
				sseg_data <= xy_data(3 downto 0);
			when others =>
				sseg_data <= "1111";
		end case;
	end process;
	
	sseg_decode: process (sseg_data)
	begin
		case sseg_data is                              -- "abcdefg"
			when "0000" => sseg_cathode <= "0000001"; -- '0'
			when "0001" => sseg_cathode <= "1001111"; -- '1'
			when "0010" => sseg_cathode <= "0010010"; -- '2'
			when "0011" => sseg_cathode <= "0000110"; -- '3'
			when "0100" => sseg_cathode <= "1001100"; -- '4'
			when "0101" => sseg_cathode <= "0100100"; -- '5'
			when "0110" => sseg_cathode <= "0100000"; -- '6'
			when "0111" => sseg_cathode <= "0001111"; -- '7'
			when "1000" => sseg_cathode <= "0000000"; -- '8'
			when "1001" => sseg_cathode <= "0000100"; -- '9'
			when "1010" => sseg_cathode <= "0001000"; -- 'A'
			when "1011" => sseg_cathode <= "1100000"; -- 'b'
			when "1100" => sseg_cathode <= "0110001"; -- 'C'
			when "1101" => sseg_cathode <= "1000010"; -- 'd'
			when "1110" => sseg_cathode <= "0110000"; -- 'E'
			when "1111" => sseg_cathode <= "0111000"; -- 'F'
			when others => sseg_cathode <= "1111111"; -- 'off'
		end case;
	end process;
	
	-- output
	sseg_an0 <= sseg_anode_data(0);
	sseg_an1 <= sseg_anode_data(1);
	sseg_an2 <= sseg_anode_data(2);
	sseg_an3 <= sseg_anode_data(3);
	sseg_ca <= sseg_cathode(6);
	sseg_cb <= sseg_cathode(5);
	sseg_cc <= sseg_cathode(4);
	sseg_cd <= sseg_cathode(3);
	sseg_ce <= sseg_cathode(2);
	sseg_cf <= sseg_cathode(1);
	sseg_cg <= sseg_cathode(0);

end rtl;