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Evaluation board with 10 Gbps Ethernet

engr_joni_ee

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I am looking for evaluation board with 10 Gbps Ethernet interfacing ? Any sugestion please ?
 
Is that the only requirement?
Flash/non-Fash based FPGAs? etc? nothing else?

I would suggest you look for a FPGA vendor which provides free to use 10GbE soft IP core and the availability of SerDes lanes on the FPGA.
 
Yes, FPGA boards are fine. I am actually interested in hardware design on PCB. Which components they use and which connector on the PCB. Any sugestion which FPGA development boards support 10gE Ethernet with schematic available ?
 
In that case you are largely limited by the Ethernet PHY for the 10G MAC core.
Out of myhead I can say that the Xilinx AC701 dev board supports 10G MAC core integration, has the appropriate SerDes lanes and on board SPF+ interface. If you find the schematic for the AC701, do take a look.
 
I am interested in ZYNQ ultrascale development board. Do they have MAC inside the ZYNQ ultrascale device ? If the MAC is inside the ZYNQ then we only need Ethernet PHY that support 10 GigE, right ?
 
@joniengr
You keep changing/upgrading your requirement with every answer of mine.
Please post all your requirements in one reply and then shall I try to answer again!
--- Updated ---


To answer your Qs:
If the MAC is inside the ZYNQ then we only need Ethernet PHY that support 10 GigE, right ?
Yes.

Do they have MAC inside the ZYNQ ultrascale device ?
Take a look inside the Zynq US device datasheet, it is an open docu and easily available through search or use the Xilinx DocNav.
 
@dpaul,

I have looked at the schematic of ZYBO Z7-020 in which they used a device from ZYNQ-7000 family, not an UltraScale device. I see that in ZYBO Z7-020, the Ethernet is 1000 M. The MAC is integrated inside the ZYNQ device and then there is a PHY chip on the development board between the Ethernet connector and the ZYNQ device.

Is that the same in UltraScale ZYNQ devices, if the device support 10 GigE then the MAC is physically present in the UltraScale ZYNQ device and we only need to consider a Ethernet PHY that support 10 GigE standard to include in the custom prototype hardware.

Can you please suggest Ethernet PHY 10 GigE that can be used with ZYNQ Ultrascale ?
 
I will give you a tip....

Search for a dev board that has an on-board SFP+ connector.
The 10G MAC core is offered as a soft IP core. Using this MAC core along with other IP cores (depending upon the connection type you want to interface) and the SFP+ connector you can handle Ethernet frames at 10G rates.
 
Hi, I am leaning about the ethernet standard 10 Gbit/s. On Wikipdia page, it says that

10 Gbit/s SFP+ is backward compatible with 1 Gbit/s SFP
Interface MAC to PHY chip is XGMII
Media: Fiber, Twisted Pair, DAC
Connector: LC and RJ45


I have a question on media and connector: do we have three media (fiber, twisted pair, DAC) to implement 10 Gbit/s ethernet on physical board ? Does it mean that we can implement 10 Gbit/s ethernet using any of the three media ? Each media (fiber, twisted pair, DAC) can support 10 Gbit/s

LC connector is used when the media is fiber
RJ45 connector is the most common ethernet cable twisted pair for copper media
Which connector do we use for DAC media ?
--- Updated ---

I will give you a tip....

Search for a dev board that has an on-board SFP+ connector.
The 10G MAC core is offered as a soft IP core. Using this MAC core along with other IP cores (depending upon the connection type you want to interface) and the SFP+ connector you can handle Ethernet frames at 10G rates.
@dpaul, I understand that 10 Gig MAC is available as a soft IP core that can be configured in Xilinx Vivado provided the ZYNQ Ultrascale support XGMII 10 Gig Ethernet. Which other chip do we need to have on the PCB between the ZYNQ and the Ethernet connector. Do we use Ethernet PHY chip on the PCB between the ZYNQ and the Ethernet connector ?
 
I think you need to first clear up some fundamentals for a FPGA based Ethernet design implementation. I recommend you to study an "Example Design from AMD":


@joniengr
secondly...
Your OP was regarding some PCB layout documents for 10G Ethernet connectivity, right?
Now I see that we have significantly deviated from that (although they are related).
For ease of management, can you please create separate threads for separate topics related to implementing 10G Ethernet using FPGAs?
 
Last edited:
Now I found some more info regarding SFP+. I have found the schematic of ZCU 102 and ZCU 106 development boards. Both use UltraScale MPSoC.

ZCU 102 has four SFP+ connectors
ZCU 106 has two SFP+ connectors

We can use any of the following three SFP + modules in SFP+ connector.
10GBASE-T SFP + Converts the SFP + end to an RJ45 connector. Designed to run on Cat 6a or better cabling, at speeds of 10Gbps.
SFP + DAC direct attach copper, very similar to the operation of a 10GBASE-T SFP + adapter, with the only difference that SFP + end is joined by a copper cable inseparable from the other end SFP +.
SFP + Fiber converts the signal received at the SFP + end to an optical signal transmitted through fiber optic cables, which allows us to reach very long distances (up to 100km) with very little delay.

Questions:
What is the speed in each SFP+ connector ? 10 Gbps or 2.5 Gbps ?
If each SFP+ connector support 10 Gbps, then it means that we can have up to 40 Gbps with four SFP+ connectors in ZCU 102 ?
And up to 20 Gbps with two SFP+ connectors in ZCU 106 ?
 

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