need help with FIFO design - the minimun FIFO depth

arunapai · Mar 6, 2009

FIFO design

Hi All,

I have a design issue, I have an interface between two domains:

Input is a 16 bit parallel data at 50MHz

Output is 1 bit serial data at 500 MHz,

For this scenario, I need to design a FIFO.

Can anyone help me with the FIFO design, especially the minimun FIFO depth?

Also I wnated to know if my input changes to a burst of 3 data units(16 bits each), what should be the depth?

Thanks,
Arun

kel8157 · Mar 6, 2009

FIFO design

If your burst is 3 beat max, then the depth should be 3 isnt it? Provided the 3 data is read out before a new burst come in. Otherwise you need to do some math, or use handshake signals to delay input burst.

Upon finishing 2nd beat, the first beat is read out completely, thus 2 data is needed, but the design is more compicated.

It also depends on over a time period how many 16b unit is accumulated in the FIFO since the read out is slower than input.

need help with FIFO design - the minimun FIFO depth

arunapai

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kel8157

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need help with FIFO design - the minimun FIFO depth

arunapai

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