arunapai
Junior Member level 2
FIFO design
Hi All,
I have a design issue, I have an interface between two domains:
Input is a 16 bit parallel data at 50MHz
Output is 1 bit serial data at 500 MHz,
For this scenario, I need to design a FIFO.
Can anyone help me with the FIFO design, especially the minimun FIFO depth?
Also I wnated to know if my input changes to a burst of 3 data units(16 bits each), what should be the depth?
Thanks,
Arun
Hi All,
I have a design issue, I have an interface between two domains:
Input is a 16 bit parallel data at 50MHz
Output is 1 bit serial data at 500 MHz,
For this scenario, I need to design a FIFO.
Can anyone help me with the FIFO design, especially the minimun FIFO depth?
Also I wnated to know if my input changes to a burst of 3 data units(16 bits each), what should be the depth?
Thanks,
Arun