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Verification Asynchronous FIFO

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xIce

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Hello everyone,

As the topic title suggests, I need to verify an Asynchronous FIFO which it can be found here;
http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf
( I believe it is famous? )

Anyway, I am completely new to the Verification world and I need to realize the System Verilog modules for every TB components (generator, driver, monitor, scoreboard, interface, transaction and model). I think I got more or less what every component does and I think I have understood the behaviour of my design, my problem I believe is how to translate everything in System Verilog.

Like, I guess there are some cases that need to be tested for the FIFO, like: 1) Read operation, 2)Write operation, 3)FIFO FULL, 4)FIFO Empty, 5) Resect active, 6)Read/Write at the same time

Knowing this, how am I supposed to translate these cases in System Verilog with a randomization test? Like, if this was a simple and normal testbench, I'd provide just the inputs and the data by myself and check on the simulation if everything works correctly, but since I need to realize those TB components, where am I supposed to start? Hope it makes sense what I mean

Thanks in advance for whoever can help me.
 

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