need help with designing QPSK modulator/demodulator

[neocool]

Hi,
I know some of the theory about BPSK and QPSK modulation. However, I am having troubles with bridging it with VHDL representation. I've tried to search the internet and all I found was mathematical models and wave representations of modulated data streams.

You need a mixer with cos and sine at the modulator side, carrier recovery, mixer filter and decision cicruitry at the receiver. How do I implement all these?

If you know anywhere I can find the example code or can just give some advices to start, please let me know.

Thanks!

 

[neocool]

I was looking in different places on internet for some examples or reference to how to bridge the theory with coding, but seems as either there people are using IP cores for all their designs of modulators, or it's very obvious, like Xilinx standart library elements and I didn't mention it.

Where should I start?
Maybe there are some books which actually show implementation? or is it patented and that's why there is no reference to the code?

I am looking for these simple types of modulation for learning purposes.

Thanks

 

[mc_navman]

There is another topic in the forums about QPSK and fsk, read that. If it is covered by patent u can go to the uspto and do a patent search, and read the patent. Patents are not secrets excatly the opposite.

 

[yeewang]

according to your questions, I don't think you're professional at HDL. Well, you'd better start with some simpler HDL design practices. It's not so hard to transfer an algorithm to HDL if you know both the algorithm and HDL well, especially when talking about a QPSK/BPSK modem. It's almost the simplest digital modulation, I think.

 

[neocool]

I am new to HDL, but done some tutorials and labs with it. I can start with something simpler like BPSK, but I need advice how to go from algorythm to vhdl code.
Also, I have read another thread on this topic. Even though it has useful information, it does not answer my particular question with bridging the gap between theory and the code.
On the patents website, I didn't find technical info regarding bpsk/qpsk modulation, just the list of sections where it is used (i.e. DSS is using bpsk).


Here is what I have simulated in matlab for BPSK. Maybe it would help to narrow down my problem and allow you to asnwer particular questions on translation from one code to another.

sr=256000.0; % Symbol rate
IPOINT=8;    % Number of oversamples
irfn=21;     % Number of filter taps          
alfs=0.5;    % Rolloff factor
[xh] = hrollfcoef(irfn,IPOINT,sr,alfs,1);   %Transmitter filter coefficients 
 
data=rand(1,nd)>0.5;  % rand: built in function
%*** BPSK Modulation 
data1=data.*2-1;  %0/1 to -1/1 translation
[data2] = oversamp( data1, nd , IPOINT) ;
data3 = conv(data2,xh);  % conv: built in function

Oversamp.m is the funciton I am using to create 8x oversampling, out is output

out=zeros(1,nd*IPOINT);
out(1:IPOINT:1+IPOINT*(nd-1))=data1

For demodulation I am using

demodata=data3 > 0; %demodata=1 if >0, demodata=0 if <0

Ignoring the filtering.. how would you translate something like that into VHDL? starting from 0/1 to -1/1 translation and oversampling..

Thank you

 

[mc_navman]

I think if you have R14 of matlab you can get it to generate hdl. I have never done this so I don't know the details.

 

[neocool]

do I need to convert 0/1 representation to -1/1 and how?

 

[mc_navman]

Actually you need to change to using integers instead of real numbers. So 0-1 will give you 2 possible values. try 0-65535.

Actually Doing this kind of design is quite involved. These signals need to be converted to real world signals as in analog.

1. Draw a block diagram. Start with the input signals and the output signals then fill in the stuff in the middle thinking about what is required.

2. come up with the specs for each of these blocks such as how many bits adc and how fast.

3. When you have a detailed desgin then you might start thinking about the hdl.

Only someone with a lot of design experience can just say I need the hdl written for this and write it scalable etc. With the questions that you are asking you are not at this level. If you can't do the inital block diagram then you don't know enough about the problem that you are trying to solve or you just don't know enough to solve it. This is not a bad thing all engineers at one time were in this position but you need to get someone who can solve this assigned to your project. You cannot do a project by asking the community on a forum unless you are close to doing it by yourself.

 

[neocool]

Thanks for the advices.
I've worked out the diagram for myself and the requirements is a serial input and 10-bit output for analog representation of the values of the BPSK stream. I think I would have ot use 2's compliment to translate data to -1/1 format. System clock is 40MHz.
1. First, the data stream has to be transformed to -1/1 format. (possibly here, the result should be 10-bit 2's compliment.
2. data stream and the sample clock have to be oversampled (number of samples should depend on the ratio of fs/fsystem).
3. Oversampled data and clock multiplied with each other - that's BPSK modulated signal.

I think I can do oversampling block and multiplication should not be too hard. I found the example codes for multiplier and the sampling should be just reading the signal at intermediate points.

If I have 40MHz system clock (square wave), then I would probably need to create sampling clock from it and represent it as a sine wave. The sine wave is going to be multiplied with translated to -1/1 and oversampled data to produce BSPK signal.

Does that sound right?

Also,

Actually you need to change to using integers instead of real numbers. So 0-1 will give you 2 possible values. try 0-65535.

I am not quite sure what you mean here. I can use 10-bit for signed 2's compliment representation of data. 2^10 gives 1024 different levels, that's +/- half if 1st bit is used for sign. Did you mean something else?

Thank you

PS
I found function generator VHDL code as well that I can use to produce the sampling sine wave.

 

[mc_navman]

What is the samples per second of your 10 bit adc?

the 0-65535 was for 16 bit. If you have a 10bit adc then you will need to scale your datat to either 0 to 1023 or -512 to + 511. When working in hdl avoid if possible using real numbers ie -1 to 1 is not what you want as this is not using intergers. It is possible to use floats and doubles (I am currently working on a FPU) but never use them if you can avoid it. To generate a sine wave use a lookup table. AM will need a multiplier on the output of your sine look up. Phase modulation will need a DDS Phase adjust register. Look up DDS techniques which are very simple to impliment in a fpga.

 

[neocool]

Ok, you ment the real range that results from division of -1/1 by 1024 symbols.. I see. Thanks! I'll take a look at DDS as well.

What I was thinking before though is that the only difference between AM and BPSK in this approach is translation of data stream from 0/1 to -1/1. Then the common part for AM and BSPK is oversample both translated data and sampling clock and then multiply the result.

Regarding ADC... where would I need ADC? I am thinking only of DAC after modulator, that can take 10-bit samples and convert it to analog form for further up conversion.


Thanks

 

[neocool]

I got BPSK working! However, I've used multiplication of the symbol clock by the data (adjusted to -1/1).
Oversampling both, the symbol clock and data with my system clock and multiplying the samples produced the desired output. I have used 5-bit words for sinewave (so 6-bits to represent in 2's compliment) and 5-bits to represent -1/1, so the answer is 11-bits 2's compliement. I guess that's what you've ment by ADC.. 5-bits resolution of the wave.

What worries me right now is that you've mentioned that AM uses multiplication, but PM uses phase adjusting register in DDS. So, that you can easily jump to the correct table value of the sinewave to represent phase shift.
Is it possible to use my implementation for further (QPSK) development? I guess I just have to use two bpsk modulators, but feed sine and cosine for Q and I channels respectively. Am I correct here? Could there be potential problems later on.. with qpsk and maybe if I go for higher order modulation techniques.

Thanks!!

 

[mc_navman]

sorry I didn't reply to your previous post, I meant to say DAC not ADC as this is used to send digital data over an analog line I guess that you must have to output an analog singnal hence the DAC.

I am guessing that you have a sine lookup table so to do QPSK you could in fact just move your pointer into the table by 90degrees worth of indexes this would give 4 phases. If you wanted to add amplitude encoding with using a multiply you could go to 1/2 and 1/4 amplitudes by right shifting the output from your lookup table ie div by 2. Except that you have 2s compliment you could still right a simple right shift that kept the sign bit in tact. Or you could use 2 lookup tables at different amplitudes and just switch between them this would be much less efficient.

Good luck.

 

[neocool]

No worries. I actually though about modulation quite a lot and figured out useful points for myself.
What you've said above sounds good. After I've created BPSK using multiply (not AM), I thought about using index shifting in sinewave LUT to realize 90deg shifts for QPSK as well. I might try it soon. But since I've done the first step using multiplication by +1 or -1, which is similar to shifting index by 0 or 180 degrees, I though maybe I could just continue with that approach and use it to create QPSK.

Here is what I am thinking about that:
I can push even bits to I channel and odd bits to Q channel. Then using the same LUT, I can adjust my table index to generate cosine and sine using two instantiations of sinewave generator block. The first one I would push into I channel block and second (sine) to Q channel block.
Each block is my bpsk modulator which I've already done.
The third step would be to add both signals.


Does it sound like a very possible implementation?


Regards.

 

[mc_navman]

Sounds possible.

 

[neocool]

Thanks,
I hope that does not create some complications later on. But hey, learning is learning!

 

[neocool]

now, I have to figure out the way to detect bpsk and qpsk signals..
I think I will need a matched filter. Also, ... need to design an AFC.
I guess it's not an easy taks. But where should I start? I saw a bunch of theory on coherent and non-coherent detectors. Same as before, it is quite tough to think of the way to implement it right away. I will start with box model describing interface of each. Which points do I need to target though?

thanks

 

[neocool]

If you wanted to add amplitude encoding with using a multiply you could go to 1/2 and 1/4 amplitudes by right shifting the output from your lookup table ie div by 2. Except that you have 2s compliment you could still right a simple right shift that kept the sign bit in tact. Or you could use 2 lookup tables at different amplitudes and just switch between them this would be much less efficient.

Good luck.

I would want to go for 16 q a m later on as well. This means there will be 3 different magnitudes and three different angles per quadrant.
1. can i just use / statement to divide LUT's values by A and B instead of doing right shift if A=2?
2. for q a m, are the other two smaller magnitudes 1/2 and 1/4 of the maximum (upper right corner of constellation) i.e. A=2, B=4? or they are some other numbers?
3. maybe it will be the best approach to write 16 cases for 16 different arrangements of 4 encoded bits per symbol of q a m? i.e. if 0001 then use specific dds register (to represent phase offset) and specific magnitude division (A, B or original max). is it a good way to approach it?

Thank you very much !
All the help that you give, guys, is greatly appreciated!

Regards

 

[udofun]

I've read all above. Thanks.
And I am going to start such emplementation too.
I need QPSK modulation and I use Altera EP20K160 fpga. So I am going to start with Verilog.
I'll write my results later.

 

[udofun]

useful. 8)
If you are interested how Altera does this:

Altera QPSK Modem Referance Design

an281.pdf

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