#### Jenna2

##### Newbie

Code:

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CSArray_multiplier is
Generic (K:integer :=8);
port ( A: in std_logic_vector (K-1 downto 0);
B: in std_logic_vector (K-1 downto 0);
P: out std_logic_vector (2*K-1 downto 0));
end CSArray_multiplier;
architecture Behavioral of CSArray_multiplier is
Component Fulladder is
port ( A: in std_logic;
B: in std_logic;
Cin: in std_logic;
Sum: out std_logic;
Carry: out std_logic);
end Component;
Signal C1: std_logic_vector (K-2 downto 0);
Component HalfAdder is
port ( A: in std_logic;
B: in std_logic;
Sum: out std_logic;
Carry: out std_logic);
end Component;
type Partial_Product_Array IS Array (K-1 downto 0) of std_logic_vector (K-1 downto 0);
Signal PP_Array,S,C: Partial_Product_Array;
Component Partial_Product is
Generic (K:integer);
port ( A: in std_logic_vector (K-1 downto 0);
B: in std_logic;
P: out std_logic_vector (K-1 downto 0));
end Component;
begin
Generate_Partial_AND: For I in 0 to K-1 generate
PP: Partial_product generic map (K=>K) port map (A=>A,B=>B(I),P=>PP_Array(I));
End Generate Generate_Partial_AND;
S(0) <= PP_Array(0);
C(0) <= (others => '0');
S(1)(K-1) <= PP_Array(1)(K-1);
C(1)(K-1) <= '0';
Generate_Half_Adder:For I in 1 to K-1 generate
HA: HalfAdder port map (A=>PP_Array(1)(I-1), B=>S(0)(I),Sum=>S(1)(I-1),Carry=>C(1)(I-1));
End Generate Generate_Half_Adder;
Generate_Full_Adder:For I in 2 to K-1 generate
S(I)(K-1) <= PP_Array(I)(K-1);
C(I)(K-1) <= '0';
Start: For J in 1 to K-1 Generate
FA: Fulladder port map (A=>PP_Array(I)(J-1), B=>S(I-1)(J),Cin=>C(I-1)(J-1),Sum=>S(I)(J-1),Carry=>C(I)(J-1));
End Generate Start;
End Generate Generate_Full_Adder;
Loop_Product: For I in 0 to K-1 Generate
P(I) <= S(I)(0);
End Generate Loop_Product;
Carry_Merge_HA: HalfAdder port map (A=>C(K-1)(0), B=>S(K-1)(1),Sum=>P(K),Carry=>C1(0));
Start: For J in 2 to K-1 Generate
CarryMergeFA: Fulladder port map(A=>C1(J-2), B=>S(K-1)(J),Cin=>C(K-1)(J-1),Sum=>P(J+K-1),Carry=>C1(J-1));
End generate Start;
P(2*K-1)<=C1(K-2);
end Behavioral;
```